LN00B096 GA MŠMT - Ministerstvo školství, mládeže a tělovýchovy
CEZ
AV0Z10750506 - UTIA-B (2005-2011)
Anotace
This paper presents an innovative tool for automatic partitioning of VHDL designs for dynamic reconfiguration called VPart. An introduction to the dynamic implementation of a circuit is presented. A design flow and optimization algorithms and methods used by the tool to partition the input design are explained. The usage of the tool is shown on three simple experiments performed on 18-bit floating-point arithmetic adder and multiplier.
