Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique

HEŘMÁNEK, A., KUNEŠ, M., TICHÝ, M. Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique. In: Proceedings of the International Conference on Field Programmable Logic and Applications. Piscataway: IEEE, 2010, s. 336-339. ISBN 978-0-7695-4179-2. Dostupné z: http://library.utia.cas.cz/separaty/2010/ZS/kunes-reducing power consumption of an embedded dsp platform through the clock-gating technique.pdf