A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project EMC2

0479509 - ÚTIA 2018 RIV CH eng C - Konferenční příspěvek (zahraniční konf.)
Isakovic, H. - Grosu, R. - Ratasich, D. - Kadlec, Jiří - Pohl, Zdeněk - Kerrison, S. … celkem 15 autorů
A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project EMC2.
Computer Safety, Reliability, and Security : SAFECOMP 2017 Workshops, ASSURE, DECSoS, SASSUR, TELERISE, and TIPS. Cham: Springer, 2017 - (Tonetta, S.; Schoitsch, E.; Bitsch, F.), s. 127-140. Lecture Notes in Computer Science, 10489. ISBN 978-3-319-66283-1. ISSN 0302-9743.
[SAFECOMP 2017 International Conference on Computer Safety, Reliability, and Security. Trento (IT), 12.09.2017-15.09.2017]
Grant CEP: GA MŠMT(BE) 7H14005
Klíčová slova: asymmetric multiprocessing * Network-on-Chip * Time-of-Flight sensor * multi-core architectures
Obor OECD: Computer hardware and architecture
http://library.utia.cas.cz/separaty/2017/ZS/kadlec-0479509.pdf

Technologies described in the paper provide hardware solution from architectural level up to the peripheral and application specific hardware. Moreover paper presents extendable multiprocessing hardware platform based on Zynq hybrid SoC, an asymmetric multiprocessing in video processing architecture, Time-of-Flight sensor and image processing architecture, predictable and verifiable Network-on-Chip (NoC), heterogeneous time-triggered NoC architecture, virtual hardware platform, software-driven energy consumption optimization techniques, and time-predictable L1 cache memory. The application of hybrid SoC platforms opposed to COTS multi-core architecture provides multiple benefits and can be seen as a viable bridging solution in the gap between single- and multi-core architectures.
Trvalý link: http://hdl.handle.net/11104/0276750