Dynamic Programmable Logic Reconfiguration for Zynq

0443453 - ÚTIA 2016 RIV CZ eng L - Prototyp, funkční vzorek
Pohl, Zdeněk
Dynamic Programmable Logic Reconfiguration for Zynq.
Interní kód: plreconf ; 2015
Technické parametry: libovolny počet bitstreamů ze SD karty
Ekonomické parametry: zvýšení funkční hustoty v FPGA obvodu
Grant CEP: GA MŠMT(BE) 7H14005
Klíčová slova: FPGA * dynamic reconfiguration * programmable logic
Kód oboru RIV: IN - Informatika
http://sp.utia.cz/index.php?ids=results&id=plreconf

The architecture of the Zynq all programmable SoC from Xilinx consists of Dual ARM Cortex-A9 cores with NEON DSP/FPU engine and of programmable logic (PL). This demo shows how the PL can be fully reconfigured without using partial dynamic reconfiguration. This way, at the cost of the longer time needed for reconfiguration of PL we can cover 90% typical applications using dynamic reconfiguration where CPU cores are running while PL adapts. The dynamic reconfiguration demo consists from two bitstreams for PL configuration and one pre-compiled software code. The software application demonstrates the PL reconfiguration. It also allows to control reset and clocks for PL. The precompiled demo prepared for ZC702 SD card can be found in boot_image/sd_card.
Trvalý link: http://hdl.handle.net/11104/0247495