FPGA implementation of the adaptive lattice filter

0411120 - UTIA-B 20030107 RIV DE eng C - Konferenční příspěvek (zahraniční konf.)
Heřmánek, Antonín - Pohl, Zdeněk - Kadlec, Jiří
FPGA implementation of the adaptive lattice filter.
Berlin: Springer, 2003. Lecture Notes in Computer Science., 2778. ISBN 3-540-40822-3. In: Field-Programmable Logic and Applications. Proceedings of the 13th International Conference. - (Cheung, P.; Constantinides, G.; de Sousa, J.), s. 1095-1098
[Field Programmable Logic and Applications /13./. Lisabon (PT), 01.09.2003-03.09.2003]
Grant CEP: GA MŠMT LN00B096
Grant ostatní: EU IST(XE) IST-2001-34016
Výzkumný záměr: CEZ:AV0Z1075907
Klíčová slova: FPGA * logarithmic numbering system * floating-point signal processor
Kód oboru RIV: JC - Počítačový hardware a software

This paper presents the FPGA implementation of a noise canceler with an adaptive RLS-Lattice filter in Xilinx devices. Since this algorithm requires floating-point computations, Logarithmic Numbering System (LNS) has been used. The pipelined lattice filter macro and input/output conversion routines has been designed. The implementation results are compared with an implementation on 32-bit IEEE floating-point signal processor.
Trvalý link: http://hdl.handle.net/11104/0131207