Utilization of the HSLA toolbox for the FPGA prototyping

0410975 - UTIA-B 20020189 RIV CZ eng C - Konferenční příspěvek (zahraniční konf.)
Pohl, Zdeněk - Líčko, M.
Utilization of the HSLA toolbox for the FPGA prototyping.
Praha: VŠCHT, 2002. ISBN 80-7080-500-5. In: MATLAB 2002. Sborník příspěvků 10. ročníku konference., s. 462-468
[MATLAB 2002. Praha (CZ), 07.11.2002]
Grant CEP: GA MŠMT LN00B096
Grant ostatní: ESPRIT(XE) 33544
Výzkumný záměr: CEZ:AV0Z1075907
Klíčová slova: design flow for DSP algorithms * high-speed logarithmic arithmetic
Kód oboru RIV: JC - Počítačový hardware a software

An innovative design-flow for DSP algorithms usign high-speed logarithmic arithmetic (HSLA) toolbox is introduced on a demo RLS lattice application. Utilization of toolbox provides effective design time shortening and it makes designer work easier. Firstly, scripts in Matlab are written and checked. From working scripts, design is decomposed in Simulink to cycle-exact simulation and rewritten in Celoxica DK1 tool. Finally, hardware is targeted from DK1 and results are compared with simulations.
Trvalý link: http://hdl.handle.net/11104/0131062