Extension for Xilinx System Generator - logarithmic arithmetic blockset

0410974 - UTIA-B 20020188 RIV CZ eng C - Konferenční příspěvek (zahraniční konf.)
Líčko, Miroslav - Métais, B. - Tichý, Milan - Matoušek, Rudolf
Extension for Xilinx System Generator - logarithmic arithmetic blockset.
Praha: VŠCHT, 2002. ISBN 80-7080-500-5. In: MATLAB 2002. Sborník příspěvků 10. ročníku konference., s. 280-284
[MATLAB 2002. Praha (CZ), 07.11.2002]
Grant CEP: GA MŠMT LN00B096
Výzkumný záměr: CEZ:AV0Z1075907
Klíčová slova: Xilinx System Generator * field programmable gate arrays * MATLAB/Simulink
Kód oboru RIV: JC - Počítačový hardware a software

The paper introduces support of floating point(FP) data format for the Xilinx System Generator (XSG) using logarithmic arithmetic. This type of arithmetic seems to be one of the promising ways to solve FP sort of DSP problems in practice. Our 32-bit high-speed logarithmic arithmetic (HSLA) keeps the accuracy according to IEEE 754 and speed up some kinds of FP algorithms. Promising is 19-bit equivalent utilised int this paper. It offers reasonable precision for the practical use and has min.HW requirements.
Trvalý link: http://hdl.handle.net/11104/0131061