Logarithmic number system and floating-point arithmetics on FPGA

0410867 - UTIA-B 20020081 RIV DE eng C - Konferenční příspěvek (zahraniční konf.)
Matoušek, Rudolf - Tichý, Milan - Pohl, Zdeněk - Kadlec, Jiří - Softley, C.
Logarithmic number system and floating-point arithmetics on FPGA.
Berlin: Springer, 2002. Lecture Notes in Computer Science., 2438. ISBN 3-540-44108-5. In: Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. - (Glesner, M.; Zipf, P.; Renovell, M.), s. 627-636
[International Conference FPL 2002 /12./. Montpellier (FR), 02.09.2002-04.09.2002]
Grant CEP: GA MŠMT LN00B096
Grant ostatní: ESPRIT(XE) 33544
Výzkumný záměr: CEZ:AV0Z1075907
Klíčová slova: LNS, DSP, QRD * FPGA, HSLA, FPU
Kód oboru RIV: JC - Počítačový hardware a software

This work has demonstrated that it is possible to design a LNS arithmetic core library of a practical word length. All main arithmetic algorithms were shown. A small case study has shown that for some applications provides the LNS solution substantially better performance while consuming a comparable area. The strengths of the LNS lies in fast multiplications, divisions, squares and square roots. It allows us to implement algorithms that are not suitable for pipelining.
Trvalý link: http://hdl.handle.net/11104/0130954