Lattice for FPGAs using logarithmic arithmetic

0410837 - UTIA-B 20020051 RIV GB eng J - Článek v odborném periodiku
Kadlec, Jiří - Matoušek, Rudolf - Heřmánek, Antonín - Líčko, Miroslav - Tichý, Milan
Lattice for FPGAs using logarithmic arithmetic.
Electronic Engineering. Roč. 74, č. 906 (2002), s. 53-56. ISSN 0013-4902
Grant ostatní: ESPRIT(XE) 33544
Výzkumný záměr: CEZ:AV0Z1075907
Klíčová slova: lattice Rls algorithm * FPGA * logarithmic arithmetic
Kód oboru RIV: JC - Počítačový hardware a software
Impakt faktor: 0.039, rok: 2002

Presented here are implementations of a complete RLS Lattice cores for Virtex. Their computational parallelism and ease of pipelining lead to easy mapping on FPGA. Internally, the computations are based on 32bit or 20bit logarithmic arithmetic (LNS). Compared are the 32bit LNS-SINGLE-ALU and 20bit LNS-QUAD-ALU versions. On Virtex XCV2000E-6, these use 27%, 54% or 40% of slices respectively and run at 50, 35 and 42 MHz on the Celoxica RC1000 board.
Trvalý link: http://hdl.handle.net/11104/0130924