0391650 - ÚTIA 2014 FR eng A - Abstrakt
Kadlec, Jiří
EDKDSP: Reprogrammable Floating Point Accelerators on KINTEX FPGA with HDMI.
2013 Design, Automation and Test in Europe. Grenoble, 2013.
[DATE 2013 Design, Automation and Test in Europe. 2013.03.18-2013.03.22, Grenoble]
Grant CEP: GA MŠMT(CZ) 7H12004
Klíčová slova: FPGA * programmable accelerators * computer video processing
Kód oboru RIV: JC - Počítačový hardware a software
Web výsledku:
http://library.utia.cas.cz/separaty/2013/ZS/kadlec-edkdsp reprogrammable floating point accelerators on kintex fpga with hdmi.pdf

Presentation of the EdkDSP reprogrammable floating point accelerators on the Xilinx Kintex FPGA (KC705) together with the HDMI video I/O (ON Semiconductor Image sensor/HDMI 1080p60). Presented SoC is using the 512 bit wide AXI-4 buses and several independent VDMA controllers.
Trvalý link: http://hdl.handle.net/11104/0221083