Reducing Power Measurements of UTIA DSP platform by Cloack-Gating Technique, Report on Experimental Results

0339887 - ÚTIA 2010 RIV CZ eng L - Prototyp, funkční vzorek
Kuneš, Michal - Heřmánek, Antonín - Tichý, Milan
Reducing Power Measurements of UTIA DSP platform by Cloack-Gating Technique, Report on Experimental Results.
Interní kód: záznam výsledku experimentu ; 2009
Technické parametry: technicka dokumentace k experimentu
Ekonomické parametry: snížení spotřeby DSP platformy
Grant CEP: GA MŠMT 7H09005
Výzkumný záměr: CEZ:AV0Z10750506
Klíčová slova: Reducing Power * UTIA DSP platform * Cloack-Gating Technique * FPGA
Kód oboru RIV: BC - Teorie a systémy řízení

With the increasing size and complexity of the today SoC systems,reduction of power consumption has become an important issue and an area of very active research. Clock gating (i.e. switching off the clock input of registers in cycles when they are not used) is one of techniques used in ASIC design to reduce dynamic power. Current FPGA devices contain multiple networks for distribution of clock signal and, in principal, allow for use of the clock gating technique. In this report, we present the results of power consumption measurements on design with and without clock gating technique on so called, which is a master-worker based multiprocessor architecture with MicroBlaze as master and a reprogrammable accelerator as worker. Since the worker may represent significant part of the overall design size, we have implemented the clock gating technique to reduce its power consumption in the IDLE time.
Trvalý link: http://hdl.handle.net/11104/0183279