Search results
- 1.0364085 - ÚTIA 2012 RIV XE eng C - Conference Paper (international conference)
Kloub, Jan - Mazanec, Tomáš - Heřmánek, Antonín
Heterogeneous Platform for Stream Based Applications on FPGAs.
Proceedings of 21st International Conference on Field Programmable Logic and Applications. Chania: IEEE, 2011, s. 401-404. ISBN 978-0-7695-4529-5.
[FPL 2011 International Conference on Field Programmable Logic and Applications (21th). Chania (GR), 05.09.2011-07.09.2011]
R&D Projects: GA MŠMT 7H09005
Institutional research plan: CEZ:AV0Z10750506
Keywords : Embedded systems * FPGA * DSP * hardware object * hardware acceleration
Subject RIV: IN - Informatics, Computer Science
http://library.utia.cas.cz/separaty/2011/ZS/kloub-heterogeneous platform for stream based applications on fpgas.pdf
Permanent Link: http://hdl.handle.net/11104/0199659 - 2.0342301 - ÚTIA 2011 RIV AT eng C - Conference Paper (international conference)
Kloub, Jan - Honzík, Petr - Daněk, Martin
Reconfigurable Hardware Objects for Image Processing on FPGAs.
Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna: Institute of Electrical and Electronics Engineers, 2010, s. 121-122. ISBN 978-1-4244-6610-8.
[Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna (AT), 14.04.2010-16.04.2010]
R&D Projects: GA MŠMT 7H09005
Institutional research plan: CEZ:AV0Z10750506
Keywords : Image Processing * Reconfiguration * Hardware Object * FPGA
Subject RIV: JC - Computer Hardware ; Software
http://library.utia.cas.cz/separaty/2010/ZS/kloub-reconfigurable hardware objects for image processing on fpgas.pdf
Permanent Link: http://hdl.handle.net/11104/0185067 - 3.0338662 - ÚTIA 2010 RIV CZ eng L - Prototype, f. module
Kloub, Jan
Graphic Computing Element Description.
Internal code: element description ; 2010
Technical parameters: Technická zpráva + CD-ROM
Economic parameters: computing element description
R&D Projects: GA MŠMT 7H09005
Institutional research plan: CEZ:AV0Z10750506
Keywords : image processing * reconfiguration * hardware object * FPGA
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0182383