Search results
- 1.0380864 - ÚTIA 2013 RIV CZ eng L4 - Software
Sýkora, Jaroslav
Optimizing C Compiler and an ELF-Based Toolchain for the PicoBlaze Processor.
Internal code: PBLAZE-CC V2 ; 2012
Technical parameters: kontakt: Jaroslav Sýkora, sykora@utia.cas.cz
Economic parameters: zvýšení produktivity programování procesoru Xilinx Picoblaze
R&D Projects: GA MŠMT(CZ) 7H10001
Grant - others:Artemis JU(XE) JU 100230
Keywords : PicoBlaze * compiler
Subject RIV: JC - Computer Hardware ; Software
http://sp.utia.cz/index.php?ids=results&id=pblazecc
Permanent Link: http://hdl.handle.net/11104/0211469 - 2.0316962 - ÚTIA 2009 RIV CZ cze L4 - Software
Svozil, Jiří - Stejskal, Jaroslav - Kafka, Leoš - Kadlec, Jiří
PicoBlaze lekce 4: Aplikace pro výuku asembleru procesoru PicoBlaze.
[PicoBlaze Lesson 4: Application for Learning Assembler of the PicoBlaze processor.]
Internal code: Tech. zpráva ; 2008
Technical parameters: Tech. zpráva + CD-ROM
Economic parameters: aplikace pro výuku
R&D Projects: GA MŠMT 2C06008
Institutional research plan: CEZ:AV0Z10750506
Keywords : PicoBlaze * FPGA
Subject RIV: IN - Informatics, Computer Science
Permanent Link: http://hdl.handle.net/11104/0166732 - 3.0316756 - ÚTIA 2009 RIV CZ eng L4 - Software
Kohout, Lukáš
Floating Point Accelerators for MicroBlaze - Partial Runtime Reconfiguration.
[Akcelerátory v pohyblivé řádové čárce pro MicroBlaze - částečná runtime rekonfigurace.]
Internal code: tech. zpráva ; 2008
Technical parameters: tech. zpráva + CD-ROM
Economic parameters: runtime rekonfigurace v FPGA
EU Projects: European Commission(XE) 027611 - AETHER
Program: FP6
Institutional research plan: CEZ:AV0Z10750506
Keywords : FPGA * MicroBlaze * PicoBlaze * floating point * partial runtime reconfiguration
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0166585 - 4.0316673 - ÚTIA 2009 RIV CZ cze L4 - Software
Stejskal, Jaroslav - Svozil, Jiří - Kafka, Leoš - Kadlec, Jiří
Řadiče periferií pro vývojovou desku Spartan3E Starter Kit.
[Peripheral Controllers for Spartan3E Starter Kit Development Board.]
Internal code: tech. zprava ; 2008
Technical parameters: tech. zpráva +CD-ROM
Economic parameters: Balíček sady modulů pro ovládání periferií
R&D Projects: GA MŠMT 2C06008
Institutional research plan: CEZ:AV0Z10750506
Keywords : PicoBlaze * FPGA
Subject RIV: IN - Informatics, Computer Science
Permanent Link: http://hdl.handle.net/11104/0166521 - 5.0310209 - ÚTIA 2009 RIV CZ cze L4 - Software
Kloub, Jan - Heřmánek, Antonín
Implementace ethernetového rozhraní s podporou protokolu UDP.
[Implementation of Ethernet interface with UDP protocol support.]
Internal code: Technicka zprava ; 2008
Technical parameters: Technicka zprava + CD
Economic parameters: implementace ethernetového rozhraní
R&D Projects: GA MŠMT(CZ) 1M0567
Keywords : Ethernet * PicoBlaze * MAC * PHY * UDP * FPGA
Subject RIV: BD - Theory of Information
Permanent Link: http://hdl.handle.net/11104/0162145 - 6.0309238 - ÚTIA 2009 RIV GB eng C - Conference Paper (international conference)
Kadlec, Jiří - Daněk, Martin - Kohout, Lukáš
Proposed architecture of configurable, adaptable SoC.
[Návrh architektury pro rekonfigurovatelné a adaptovatelné systémy na jednom čipu.]
The IET Irish Signals and Systems Conference ISSC 2008. Londýn: Institution of Engineering and Technology, 2008 - (Morgan, F.; Glavin, M.; Jones, E.), s. 368-373. ISBN 978-0-86341-931-7.
[The Institution of Engineering and Technology Irish Signals and Systems Conference, ISSC 2008. Galway (IE), 18.06.2008-19.06.2008]
R&D Projects: GA MŠMT 2C06008
EU Projects: European Commission(XE) 027611 - AETHER
Program: FP6
Institutional research plan: CEZ:AV0Z10750506
Keywords : MicroBlaze * PicoBlaze * floating point accelerators * runtime reconfiguration
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0161437 - 7.0093189 - ÚTIA 2008 RIV CZ cze L - Prototype, f. module
Kloub, Jan - Heřmánek, Antonín
Implementace akcelerátorů pro dekódování konvolučního a Reed-Solomonova zabezpečovacího kódu na obvodech FPGA.
[Implementation of Accelerators for Decoding Reed-Solomon and Convolution error-correcting code on FPGA.]
Internal code: Akcelerátory na obvodech FPGA ; 2007
Technical parameters: 1 cd
Economic parameters: programová impementace akcelerátorů
R&D Projects: GA AV ČR 1ET100750408; GA AV ČR 1ET300750402
Institutional research plan: CEZ:AV0Z10750506
Keywords : FPGA * Reed-Solomon encoder * Reed-Solomon decoder * PicoBlaze processor * Ethernet * Viterbi decoder * FEC * Convolution code * Error-correcting code
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0153297 - 8.0090568 - ÚTIA 2008 HU eng A - Abstract
Kadlec, Jiří
Embedded Development Environment for a Family of Xilinx FPGA.
[Prostředí pro návrh vestavných systémů na programovatelných obvodech Xilinx.]
Regional Conference on Embedded and Ambient Systems Book of Abstracts. Budapešť: John von Neumann Computer Society, 2007 - (Varga, A.; Kiss, Á.; Marsiske, S.; Vásárhelyi, J.). s. 16-16. ISBN 978-963-8431-96-7.
[RCEAS 2007 First Regional Conference on Embedded and Ambient Systems. 22.11.2007-24.11.2007, Budapešť]
R&D Projects: GA MŠMT(CZ) 1M0567; GA AV ČR 1ET400750406
EU Projects: European Commission(XE) 027611 - AETHER
Program: FP6
Institutional research plan: CEZ:AV0Z10750506
Keywords : FPGA * PicoBlaze * Embedded systems
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0151422 - 9.0083363 - ÚTIA 2008 RIV CZ cze E - Electronic Document
Svozil, Jiří - Stejskal, Jaroslav - Kafka, Leoš - Kadlec, Jiří
PicoBlaze lekce 3: sériová komunikace RS232 a testování IP jader pomocí procesoru PicoBlaze.
[PicoBlaze lesson 3: serial communication RS232 and testing IP cores by PicoBlaze processor.]
[program]. - Praha: ÚTIA AV ČR, 2007, 9MB
R&D Projects: GA MŠMT 2C06008
Institutional research plan: CEZ:AV0Z10750506
Keywords : PicoBlaze * IP cores * serial communication
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0146627 - 10.0081306 - ÚTIA 2007 RIV CZ cze E - Electronic Document
Heřmánek, Antonín - Dušek, J. - Kloub, Jan
Demonstrátor Reed-Solomonova kodéru a dekodéru s ethernetovým rozhraním implentovaný v FPGA.
[FPGA implementation of demonstrator of Reed-Solomon encoder and decoder with ethernet interface.]
[program]. - Praha: ÚTIA AV ČR, 2007, 16,5 MB
R&D Projects: GA AV ČR 1ET100750408
Institutional research plan: CEZ:AV0Z10750506
Keywords : FPGA * Reed-Solomon encoder * Reed-Solomon decoder * PicoBlaze processor
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0145221