Search results
- 1.0429947 - ÚTIA 2015 RIV US eng M - Monography Chapter
Bartosinski, Roman - Daněk, Martin - Kafka, Leoš - Kohout, Lukáš - Sýkora, Jaroslav
The Architecture and the Technology Characterization of an FPGA-Based Customizable Application-Specific Vector Coprocessor (ASVP).
Smart Multicore Embedded Systems. New York: Springer, 2014 - (Massimo, T.; Bertels, K.; Karlsson, S.; Pacull, F.), s. 45-77. ISBN 978-1-4614-8799-9
R&D Projects: GA MŠMT(CZ) 7H10001
Keywords : custom accelerators * vector processing * FPGA * DSP
Subject RIV: JC - Computer Hardware ; Software
http://link.springer.com/chapter/10.1007/978-1-4614-8800-2_4
Permanent Link: http://hdl.handle.net/11104/0235497 - 2.0410975 - UTIA-B 20020189 RIV CZ eng C - Conference Paper (international conference)
Pohl, Zdeněk - Líčko, M.
Utilization of the HSLA toolbox for the FPGA prototyping.
Praha: VŠCHT, 2002. ISBN 80-7080-500-5. In: MATLAB 2002. Sborník příspěvků 10. ročníku konference., s. 462-468
[MATLAB 2002. Praha (CZ), 07.11.2002]
R&D Projects: GA MŠMT LN00B096
Grant - others:ESPRIT(XE) 33544
Institutional research plan: CEZ:AV0Z1075907
Keywords : design flow for DSP algorithms * high-speed logarithmic arithmetic
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0131062 - 3.0410916 - UTIA-B 20020130 RIV US eng C - Conference Paper (international conference)
Albu, F. - Kadlec, Jiří - Coleman, N. - Fagan, A.
Pipelined implementations of the A Priory Error-Feedback LSL algorithm using logarithmic arithmetic.
Orlando: IEEE, 2002. ISBN 0-7803-7403-7. In: Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing., s. 2681-2684
[ICASSP 2002. Orlando (US), 13.05.2002-17.05.2002]
Grant - others:ESPRIT(XE) 33544
Institutional research plan: CEZ:AV0Z1075907
Keywords : LNS, DSP, FPGA * floating-point * logarithmic arithmetic
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0131003 - 4.0410868 - UTIA-B 20020082 RIV CZ eng C - Conference Paper (international conference)
Matoušek, Rudolf - Líčko, Miroslav - Heřmánek, Antonín - Softley, C.
Floating-Point-Like Arithmetic for FPGA.
Praha: FEL ČVUT, 2002. In: POSTER 2002., s. 2
[International Student Conference on Electrical Engineering /6./. Praha (CZ), 23.05.2002]
R&D Projects: GA MŠMT LN00B096
Grant - others:ESPRIT(XE) 33544
Institutional research plan: CEZ:AV0Z1075907
Keywords : HSLA, RLS, LNS * IP core, DSP
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0130955 - 5.0410867 - UTIA-B 20020081 RIV DE eng C - Conference Paper (international conference)
Matoušek, Rudolf - Tichý, Milan - Pohl, Zdeněk - Kadlec, Jiří - Softley, C.
Logarithmic number system and floating-point arithmetics on FPGA.
Berlin: Springer, 2002. Lecture Notes in Computer Science., 2438. ISBN 3-540-44108-5. In: Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. - (Glesner, M.; Zipf, P.; Renovell, M.), s. 627-636
[International Conference FPL 2002 /12./. Montpellier (FR), 02.09.2002-04.09.2002]
R&D Projects: GA MŠMT LN00B096
Grant - others:ESPRIT(XE) 33544
Institutional research plan: CEZ:AV0Z1075907
Keywords : LNS, DSP, QRD * FPGA, HSLA, FPU
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0130954 - 6.0410866 - UTIA-B 20020080 RIV CZ eng C - Conference Paper (international conference)
Líčko, Miroslav - Tichý, Milan - Heřmánek, Antonín - Matoušek, Rudolf - Pohl, Zdeněk
Prototyping of DSP algorithms on FPGA.
Praha: FEL ČVUT, 2002. In: POSTER 2002., s. 2
[International Student Conference on Electrical Engineering /6./. Praha (CZ), 23.05.2002]
R&D Projects: GA MŠMT LN00B096
Institutional research plan: CEZ:AV0Z1075907
Keywords : DSP * FPGA * floating-point
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0130953 - 7.0380442 - ÚTIA 2013 RIV TR eng C - Conference Paper (international conference)
Sýkora, Jaroslav - Bartosinski, Roman - Kohout, Lukáš - Daněk, Martin - Honzík, P.
Reducing Instruction Issue Overheads in Application-Specific Vector Processors.
Proceedings of the 15th Euromicro Conference on Digital System Design, DSD 2012. Izmir: Conference Publishing Services, 2012 - (Niar, S.), s. 600-607. ISBN 978-0-7695-4798-5.
[15th Euromicro Conference on Digital System Design. Cesme (TR), 05.09.2012-08.09.2012]
R&D Projects: GA MŠMT(CZ) 7H10001
Grant - others:Commission EU(XE) Artemis JU 100230
Keywords : custom accelerators * vector processing * FPGA * DSP
Subject RIV: JC - Computer Hardware ; Software
http://library.utia.cas.cz/separaty/2012/ZS/sykora-reducing instruction issue overheads in application-specific vector processors.pdf
Permanent Link: http://hdl.handle.net/11104/0211153 - 8.0364085 - ÚTIA 2012 RIV XE eng C - Conference Paper (international conference)
Kloub, Jan - Mazanec, Tomáš - Heřmánek, Antonín
Heterogeneous Platform for Stream Based Applications on FPGAs.
Proceedings of 21st International Conference on Field Programmable Logic and Applications. Chania: IEEE, 2011, s. 401-404. ISBN 978-0-7695-4529-5.
[FPL 2011 International Conference on Field Programmable Logic and Applications (21th). Chania (GR), 05.09.2011-07.09.2011]
R&D Projects: GA MŠMT 7H09005
Institutional research plan: CEZ:AV0Z10750506
Keywords : Embedded systems * FPGA * DSP * hardware object * hardware acceleration
Subject RIV: IN - Informatics, Computer Science
http://library.utia.cas.cz/separaty/2011/ZS/kloub-heterogeneous platform for stream based applications on fpgas.pdf
Permanent Link: http://hdl.handle.net/11104/0199659 - 9.0341115 - ÚTIA 2011 RIV US eng J - Journal Article
Tichý, Milan - Schier, Jan - Gregg, D.
GSFAP Adaptive Filtering Using Log Arithmetic for Resource-Constrained Embedded Systems.
ACM Transactions on Embedded Computing Systems. Roč. 9, č. 3 (2010), s. 1-31. ISSN 1539-9087. E-ISSN 1558-3465
R&D Projects: GA MŠMT 7H09005
Institutional research plan: CEZ:AV0Z10750506
Keywords : FPGA * DSP * logarithmic arithmetic * affine projection
Subject RIV: BD - Theory of Information
Impact factor: 1.057, year: 2010
http://library.utia.cas.cz/separaty/2010/ZS/tichy-0341115.pdf
Permanent Link: http://hdl.handle.net/11104/0184199 - 10.0339887 - ÚTIA 2010 RIV CZ eng L - Prototype, f. module
Kuneš, Michal - Heřmánek, Antonín - Tichý, Milan
Reducing Power Measurements of UTIA DSP platform by Cloack-Gating Technique, Report on Experimental Results.
Internal code: záznam výsledku experimentu ; 2009
Technical parameters: technicka dokumentace k experimentu
Economic parameters: snížení spotřeby DSP platformy
R&D Projects: GA MŠMT 7H09005
Institutional research plan: CEZ:AV0Z10750506
Keywords : Reducing Power * UTIA DSP platform * Cloack-Gating Technique * FPGA
Subject RIV: BC - Control Systems Theory
Permanent Link: http://hdl.handle.net/11104/0183279