Search results
- 1.0382326 - ÚTIA 2013 RIV NL eng C - Conference Paper (international conference)
Van Tol, M. W. - Pohl, Zdeněk - Tichý, Milan
A Framework for Self-adaptive Collaborative Computing on Reconfigurable Platforms.
Advances in Parallel Computing. Amsterdam: IOS Press BV, 2012, s. 579-586. ISBN 978-1-61499-040-6.
[International Conference on Parallel Computing. Ghent (BE), 30.08.2011-02.09.2011]
EU Projects: European Commission(XE) 027611 - AETHER
Program: FP6
Institutional support: RVO:67985556
Keywords : distributed systems * collaborative computing * resource management * heterogeneous systems * adaptive systems * SVP * MicroBlaze * FPGA
Subject RIV: IN - Informatics, Computer Science
http://library.utia.cas.cz/separaty/2012/ZS/pohl-0382326.pdf
Permanent Link: http://hdl.handle.net/11104/0212577 - 2.0313340 - ÚTIA 2009 RIV DE eng C - Conference Paper (international conference)
Daněk, Martin - Philippe, J.-M. - Bartosinski, Roman - Honzík, Petr - Gamrat, Ch.
Self-Adaptive Networked Entities for Building Pervasive Computing Aschitectures.
[Samoadaptivní síťová entita pro stavbu pervasivních počítačových architektur.]
International Conference on Evolvable Systems: From Biology to Harware, 8th International Conference, ICES 2008. Heidelberg: Springer, 2008 - (Hornby, G.; Sekanina, L.; Haddow, P.), s. 94-105. ISBN 978-3-540-85856-0. ISSN 0302-9743.
[International Conference on Evolvable Systems: From Biology to Harware, 8th International Conference, ICES 2008. Praha (CZ), 22.09.2008-24.09.2008]
R&D Projects: GA MŠMT(CZ) 1M0567
EU Projects: European Commission(XE) 027611 - AETHER
Program: FP6
Institutional research plan: CEZ:AV0Z10750506
Keywords : Self-adaptation * FPGA * Simulink
Subject RIV: BD - Theory of Information
http://library.utia.cas.cz/separaty/2008/ZS/danek-self-adaptive networked entities for building pervasive computing aschitectures.pdf
Permanent Link: http://hdl.handle.net/11104/0164192 - 3.0313274 - ÚTIA 2009 RIV DE eng C - Conference Paper (international conference)
Daněk, Martin - Kadlec, Jiří - Bartosinski, Roman - Kohout, Lukáš
Increasing the Level of Abstraction in FPGA-based Designes.
[Zvyšování úrovně abstrakce v návrzích založených na FPGA.]
International Conference on Field Programmable Logic and Applications. Heidelberg: Kirchhoff Institute for Physics, 2008 - (Kebschull, U.), s. 5-10. ISBN 978-1-4244-1961-6.
[International Conference on Field Programmable Logic and Applications. Heidelberg (DE), 08.09.2008-10.09.2008]
EU Projects: European Commission(XE) 027611 - AETHER
Program: FP6
Institutional research plan: CEZ:AV0Z10750506
Keywords : FPGA * dataflow * floating-point
Subject RIV: JC - Computer Hardware ; Software
http://library.utia.cas.cz/separaty/2008/ZS/danek-increasing%20the%20level%20of%20abstraction%20in%20fpga-based%20designes.pdf
Permanent Link: http://hdl.handle.net/11104/0164145 - 4.0309238 - ÚTIA 2009 RIV GB eng C - Conference Paper (international conference)
Kadlec, Jiří - Daněk, Martin - Kohout, Lukáš
Proposed architecture of configurable, adaptable SoC.
[Návrh architektury pro rekonfigurovatelné a adaptovatelné systémy na jednom čipu.]
The IET Irish Signals and Systems Conference ISSC 2008. Londýn: Institution of Engineering and Technology, 2008 - (Morgan, F.; Glavin, M.; Jones, E.), s. 368-373. ISBN 978-0-86341-931-7.
[The Institution of Engineering and Technology Irish Signals and Systems Conference, ISSC 2008. Galway (IE), 18.06.2008-19.06.2008]
R&D Projects: GA MŠMT 2C06008
EU Projects: European Commission(XE) 027611 - AETHER
Program: FP6
Institutional research plan: CEZ:AV0Z10750506
Keywords : MicroBlaze * PicoBlaze * floating point accelerators * runtime reconfiguration
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0161437 - 5.0085964 - ÚTIA 2010 RIV NL eng C - Conference Paper (international conference)
Kadlec, Jiří - Bartosinski, Roman - Daněk, Martin
Accelerating MicroBlaze Floating Point Operations.
[Akcelerace operací v pohyblivé čárce pro MicroBlaze.]
Proceedings 2007 International Conference on Field Programmable Logic and Applications (FPL). Delft: IEEE, 2007 - (Bertels, K.; Najjar, W.; Genderen, A.; Vassiliadis, S.), s. 621-624. ISBN 978-1-4244-1059-0; ISBN 1-4244-1060-6.
[International Conference on Field Programmable Logic and Applications. FPL 2007. Amsterdam (NL), 27.08.2007-29.08.2007]
R&D Projects: GA AV ČR 1ET400750406; GA MŠMT(CZ) 1M0567
EU Projects: European Commission(XE) 027611 - AETHER
Program: FP6
Institutional research plan: CEZ:AV0Z10750506
Keywords : acceleration * floating point operation * coprocessor * MicroBlaze
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0004136 - 6.0085945 - ÚTIA 2010 RIV NL eng C - Conference Paper (international conference)
Pohl, Zdeněk - Tichý, Milan
RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator.
[RLS Lattice rozšířený o odhad pravěpodobnosti řádu jako akcelerátor.]
Proceedings 2007 International Conference on Field Programmable Logic and Applications (FPL). Delft: IEEE, 2007 - (Bertels, K.; Najjar, W.; Genderen, A.; Vassiliadis, S.), s. 774-777. ISBN 978-1-4244-1059-0; ISBN 1-4244-1060-6.
[International Conference on Field Programmable Logic and Applications. FPL 2007. Amsterdam (NL), 27.08.2007-29.08.2007]
R&D Projects: GA MŠMT(CZ) 1M0567
EU Projects: European Commission(XE) 027611 - AETHER
Program: FP6
Institutional research plan: CEZ:AV0Z10750506
Keywords : DSP * adaptive filter * logarithmic arithmetic * embedded processor * FPGA
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0004135 - 7.0040204 - ÚTIA 2007 RIV CZ eng C - Conference Paper (international conference)
Kadlec, Jiří - Daněk, Martin
Design and verification methodology for reconfigurable designs in Atmel FPSLIC.
[Metody návrhu a verifikace pro rekonfigurovatelné návrhy v obvodu Atmel FPSLIC.]
Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits adn Systems. Prague: Czech Technical University, 2006 - (Reorda, M.; Novák, O.; Straube, B.), s. 79-80. ISBN 1-4244-0184-4.
[DDECS 2006. IEEE Design and Diagnostics of Electronic Circuits and Systems. Prague (CZ), 18.04.2006-21.04.2006]
R&D Projects: GA ČR GA102/04/2137
EU Projects: European Commission(XE) 027611 - AETHER
Grant - others:Commission EC(XE) IST-2001-34016
Program: FP6
Institutional research plan: CEZ:AV0Z10750506
Keywords : FPGA * dynamic reconfiguration * FPSLIC * floating-point IP cores * design flow
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0134004