Search results
- 1.0411001 - UTIA-B 20020215 CZ eng V - Research Report
Líčko, Miroslav - Schier, Jan - Pohl, Zdeněk - Kadlec, Jiří - Tichý, Milan - Matoušek, Rudolf - Heřmánek, Antonín
Logarithmic Arithmetic for Real Data Types and Support for MATLAB/SIMULINK Based Rapid-FPGA-Prototyping.
Praha: ÚTIA AV ČR, 2002. 7 s. Research Report, 2069.
R&D Projects: GA MŠMT LN00B096
Institutional research plan: CEZ:AV0Z1075907
Keywords : rapid prototyping for FPGA * MATLAB/Simulink
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0131088 - 2.0410736 - UTIA-B 20010205 CZ eng V - Research Report
Coleman, J. N. - Kadlec, Jiří - Matoušek, Rudolf - Pohl, Zdeněk - Heřmánek, Antonín
The European Logarithmic Microprocessor - a QRD RLS Applications.
Praha: ÚTIA AV ČR, 2001. 9 s. Research Report, 2038.
R&D Projects: GA MŠMT LN00B096
Grant - others:ESPRIT(XE) HSLA 33544
Institutional research plan: AV0Z1075907
Keywords : logarithmic number system * digital signal processing
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0130824 - 3.0106372 - UTIA-B 20040184 CZ eng V - Research Report
Pohl, Zdeněk - Heřmánek, Antonín
ADPCM IP Cores.
Praha: ÚTIA AV ČR, 2004. 4 s. Research Report, 2109.
R&D Projects: GA MŠMT LN00B096
Grant - others:RECONF2(XE) IST-2001-34016
Institutional research plan: CEZ:AV0Z1075907
Keywords : FPGA * dynamic reconfiguration * embedded HW
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0013554 - 4.0106371 - UTIA-B 20040183 CZ eng V - Research Report
Pohl, Zdeněk - Heřmánek, Antonín
ADPCM Demo.
Praha: ÚTIA AV ČR, 2004. 4 s. Research Report, 2108.
R&D Projects: GA MŠMT LN00B096
Grant - others:RECONF2(XE) IST-2001-34016
Institutional research plan: CEZ:AV0Z1075907
Keywords : FPGA * dynamic reconfiguration * embedded HW
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0013553