Search results
- 1.0411362 - UTIA-B 20050092 RIV US eng J - Journal Article
Matoušek, Rudolf - Daněk, Martin - Pohl, Zdeněk - Bartosinski, Roman - Honzík, Petr
Reconfigurable System-on-a-Chip.
[Rekonfigurovatelné systémy na jediném čipu.]
Syndicated. Roč. 5, č. 2 (2005), s. 1-3
R&D Projects: GA AV ČR 1ET400750406; GA AV ČR 1QS108040510; GA AV ČR 1ET400750408
Institutional research plan: CEZ:AV0Z10750506
Keywords : FPGA * dynamic reconfiguratio * system-on-chip
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0131444 - 2.0411292 - UTIA-B 20050020 RIV US eng J - Journal Article
Daněk, Martin - Honzík, Petr - Kadlec, Jiří - Matoušek, Rudolf - Pohl, Zdeněk
Reconfigurable system on programmable chip platform.
[Rekonfigurovatelný systém pro programovatelný integrovaný obvod.]
ATMEL Applications Journal. č. 4 (2005), s. 9-12
R&D Projects: GA ČR GA102/04/2137
Grant - others:EU FP5 IST Programme(XE) IST-2001-34016
Institutional research plan: CEZ:AV0Z10750506
Keywords : reconfigurable system * FPGA
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0131375 - 3.0312228 - ÚTIA 2009 RIV US eng J - Journal Article
Pohl, Zdeněk - Tichý, Milan - Kadlec, Jiří
Implementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA.
[Implementace příčkového algoritmu nejmenších čtverců s odhadem řádu a zapomínaní pro FPGA.]
EURASIP Journal on Advances in Signal Processing. Roč. 2008, č. 2008 (2008), s. 1-11. ISSN 1687-6172
R&D Projects: GA MŠMT(CZ) 1M0567
EU Projects: European Commission(XE) 027611 - AETHER
Program: FP6
Institutional research plan: CEZ:AV0Z10750506
Keywords : DSP * Least-squares lattice * order estimation * exponential forgetting factor estimation * FPGA implementation * scheduling * dynamic reconfiguration * microblaze
Subject RIV: IN - Informatics, Computer Science
Impact factor: 1.055, year: 2008
http://library.utia.cas.cz/separaty/2008/ZS/pohl-tichy-kadlec-implementation%20of%20the%20least-squares%20lattice%20with%20order%20and%20forgetting%20factor%20estimation%20for%20fpga.pdf
Permanent Link: http://hdl.handle.net/11104/0163345 - 4.0085961 - ÚTIA 2008 RIV US eng J - Journal Article
Coleman, J. N. - Softley, C. I. - Kadlec, Jiří - Matoušek, R. - Tichý, Milan - Pohl, Zdeněk - Heřmánek, Antonín - Benschop, N. F.
The European Logarithmic Microprocessor.
[Evropský logaritmický mikroprocesor.]
IEEE Transactions on Computers. Roč. 57, č. 4 (2008), s. 532-546. ISSN 0018-9340. E-ISSN 1557-9956
Grant - others:Evropská komise(BE) ESPRIT 33544
Institutional research plan: CEZ:AV0Z10750506
Source of funding: R - Framework programmes of European Commission
Keywords : Processor architecture * arithmetic unit * logarithmic arithmetic
Subject RIV: JC - Computer Hardware ; Software
Impact factor: 2.611, year: 2008
http://library.utia.cas.cz/separaty/2008/ZS/kadlec-the%20european%20logarithmic%20microprocessor.pdf
Permanent Link: http://hdl.handle.net/11104/0148357 - 5.0039044 - ÚTIA 2007 RIV CZ cze J - Journal Article
Daněk, Martin - Honzík, Petr - Kadlec, Jiří - Pohl, Zdeněk - Matoušek, Rudolf
Platforma s částečnou dynamickou rekonfigurací FPGA.
[Reconfigurable System-on-a-Programable-Chip Platform.]
Automa. Roč. 12, č. 5 (2006), s. 40-43. ISSN 1210-9592
R&D Projects: GA ČR GA102/04/2137
Grant - others:Commisions EC(XE) IST-2001-34016
Institutional research plan: CEZ:AV0Z10750506
Keywords : FPGA * dynamic reconfiguration * SoC
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0133224