Search results
- 1.0316050 - ÚTIA 2009 RIV CZ eng C - Conference Paper (international conference)
Kovář, Bohumil - Kloub, Jan - Schier, Jan - Heřmánek, Antonín
Rapid Prototyping Platform For Reconfigurable Image Processing.
[Platforma pro rychlý vývoj rekonfigurovatelného zpracování obrazu.]
Technical computing Prague 2008. 16th annual conference proceedings. Praha: Humusoft, 2008, s. 62-62. ISBN 978-80-7080-692-0.
[Technical Computing Prague 2008 /16./. Praha (CZ), 11.11.2008-11.11.2008]
R&D Projects: GA AV ČR 1ET400750408
Institutional research plan: CEZ:AV0Z10750506
Keywords : reconfiguration * image processing * FPGA * DSP
Subject RIV: JC - Computer Hardware ; Software
http://library.utia.cas.cz/separaty/2008/ZS/kovar-rapid prototyping platform for reconfigurable image processing.pdf
Permanent Link: http://hdl.handle.net/11104/0166089 - 2.0106326 - UTIA-B 20040138 RIV DE eng C - Conference Paper (international conference)
Schier, Jan - Heřmánek, Antonín
Using logarithmic arithmetic to implement the Recursive Least Squares (QR) algorithm in FPGA.
[Použití logaritmické aritmetiky pro implementaci výpočtu rekurzivních nejmenších čtverců v FPGA obvodu.]
Field-Programmable Logic and Applications. 14th International Conference FPL 2004. Proceedings. Berlin: Springer, 2004 - (Becker, J.; Platzner, M.; Vernalde, S.), s. 1149-1151. Lecture Notes in Computer Science., 3203. ISBN 3-540-22989-2.
[International Conference FPL 2004 /14./. Antverp (BE), 30.08.2004-01.09.2004]
R&D Projects: GA MŠMT LN00B096; GA AV ČR 1ET400750408; GA AV ČR 1ET300750402
Institutional research plan: CEZ:AV0Z1075907
Keywords : QR update * FPGA * logarithmic arithmetic
Subject RIV: BD - Theory of Information
Permanent Link: http://hdl.handle.net/11104/0013508 - 3.0106325 - UTIA-B 20040137 RIV AT eng C - Conference Paper (international conference)
Heřmánek, Antonín - Schier, Jan - Regalia, P.
Architecture design for FPGA implementation of finite interval CMA.
[Návrh architektury pro FPGA implementaci blokového CMA algoritmu (Finite interval CMA).]
Proceedings of the 12th European Signal Processing Conference. Vienna: University of Technology, 2004 - (Hlawatsch, F.; Matz, G.; Rupp, M.), s. 1-4. ISBN 3-200-00165-8.
[EUSIPCO 2004 /12./. Vienna (AT), 06.09.2004-10.09.2004]
R&D Projects: GA MŠMT LN00B096; GA AV ČR 1ET300750402; GA AV ČR 1ET400750408
Institutional research plan: CEZ:AV0Z1075907
Keywords : blind equalization * CMA, FPGA * logarithmic arithmetic
Subject RIV: BD - Theory of Information
Permanent Link: http://hdl.handle.net/11104/0013507 - 4.0098562 - ÚTIA 2008 RIV SK eng C - Conference Paper (international conference)
Schier, Jan - Kovář, Bohumil - Zuzaňák, J.
Configuration System for a DSP/FPGA-Based Embedded Accelerator.
[Konfigurační systém pro vestavěný DSP/FPGA akcelerátor.]
Digital Technologies 2007 Proceedings. Žilina: Slovenská elektrotechnická spoločnosť, 2007 - (Jarina, R.), s. 1-4. ISBN 978-80-8070-786-6.
[Digital Technologies 2007. Žilina (SK), 29.11.2007-30.11.2007]
R&D Projects: GA AV ČR 1ET400750408
Institutional research plan: CEZ:AV0Z10750506
Keywords : video-processing * FPGA * accelerator * configuration * Simulink
Subject RIV: JB - Sensors, Measurment, Regulation
Permanent Link: http://hdl.handle.net/11104/0157439 - 5.0090120 - ÚTIA 2008 RIV CZ eng C - Conference Paper (international conference)
Kovář, Bohumil - Schier, Jan - Zemčík, P. - Herout, A. - Zuzaňák, J.
Simulink Model Converter for Embedded Video Accelerator.
[Konvertor Simulinkových modelů pro vestavěný videoakcelerátor.]
Technical Computing Prague 2007. Praha: Humusoft, 2007, s. 79-79. ISBN 978-80-7080-658-6.
[Technical Computing Prague 2007. Praha (CZ), 14.11.2007-14.11.2007]
R&D Projects: GA AV ČR 1ET400750408
Institutional research plan: CEZ:AV0Z10750506
Keywords : image processing accelerator * Simulink * configuration engine * Simulink conversion
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0151121 - 6.0076044 - ÚTIA 2007 RIV SK eng C - Conference Paper (international conference)
Schier, Jan - Kovář, Bohumil
A DSP/FPGA-based accelerator for video.
[Video akcelerátor, založený na FPGA/DSP architektuře.]
Digital Technologies 2006. Žilina: Slovenská elektrotechnická spoločnosť, 2006, s. 1-5.
[Digital Technologies 2006. Žilina (SK), 01.12.2006]
R&D Projects: GA AV ČR 1ET400750408
Institutional research plan: CEZ:AV0Z10750506
Keywords : video processing * hardware acceleration * configuration system
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0143245 - 7.0030415 - ÚTIA 2007 RIV EG eng C - Conference Paper (international conference)
Zemčík, P. - Herout, A. - Beran, V. - Fučík, A. - Schier, Jan
Reconfigurable image processing architecture.
[Rekonfigurovatelná architektura pro zpracování obrazu.]
ICGST International Conference on Graphics, Vision and Image Processing. GVIP-05. Káhira: ICGST, 2005, s. 1-6.
[International Conference on Graphics, Vision and Image Processing. Káhira (EG), 19.12.2005-21.12.2005]
R&D Projects: GA AV ČR(CZ) 1ET400750408
Institutional research plan: CEZ:AV0Z10750506
Keywords : image processing * DSP * FPGA * scripting
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0120156 - 8.0026140 - ÚTIA 2006 RIV CZ eng C - Conference Paper (international conference)
Schier, Jan - Kovář, Bohumil - Zemčík, P. - Herout, A. - Beran, V.
Reconfigurable image processing architecture with simulink prototyping support.
[Rekonfigurovatelná architektura pro zpracování obrazu s podporou rychlého modelování v Simulinku.]
Technical Computing Prague 2005. 13th Annual Conference Proceeding. Praha: VŠCHT, 2005 - (Moler, C.; Procházka, A.; Walden, B.), s. 1-4. ISBN 80-7080-577-3.
[MATLAB 05. Annual Conference of Technical Computing Prague 2005 /13./. Praha (CZ), 15.11.2005]
R&D Projects: GA AV ČR(CZ) 1ET400750408
Institutional research plan: CEZ:AV0Z10750506
Keywords : embedded image processing * FPGA * DSP
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0116433