Search results
- 1.0411508 - ÚTIA 2010 RIV GR eng C - Conference Paper (international conference)
Heřmánek, Antonín - Schier, Jan - Šůcha, P. - Hanzálek, Z.
Optimization of finite interval CMA implementation for FPGA.
[Optimalizace FPGA implementace FI-CMA algoritmu.]
0-7803-9334-1. In: Proceedings of the IEEE Workshop on Signal Processing Systems. SiPS 2005. Athens: IEEE, 2005, s. 1-6. ISBN 0-7803-9333-3.
[SiPS 2005. IEEE Workshop on Signal Processing Systems. Athens (GR), 02.11.2005-04.11.2005]
R&D Projects: GA AV ČR 1ET300750402; GA MŠMT 1M0567
Institutional research plan: CEZ:AV0Z10750506
Keywords : CMA * FPGA * logarithmic arithmetic * cyclic scheduling
Subject RIV: BD - Theory of Information
Permanent Link: http://hdl.handle.net/11104/0131588 - 2.0411312 - ÚTIA 2010 RIV BE eng C - Conference Paper (international conference)
Heřmánek, Antonín - Schier, Jan
FPGA implementation of Finite Interval CMA.
[FPGA implementace FI-CMA algoritmu.]
Antverpy: IEEE, 2005. In: Proceedings of the first annual IEEE BENELUX/DSP Valley Signal Processing Symposium. SPS-DARTS 2005. Antverpy: IEEE, 2005, s. 97-100. ISBN 0-7803-9333-3.
[SPS-DARTS 2005 Signal Processing Symposium /1./. Antverpy (BE), 19.04.2005-20.04.2005]
R&D Projects: GA AV ČR 1ET300750402
Institutional research plan: CEZ:AV0Z10750506
Keywords : CMA algorithm * FPGA * data matrix
Subject RIV: JA - Electronics ; Optoelectronics, Electrical Engineering
Permanent Link: http://hdl.handle.net/11104/0131395 - 3.0106326 - UTIA-B 20040138 RIV DE eng C - Conference Paper (international conference)
Schier, Jan - Heřmánek, Antonín
Using logarithmic arithmetic to implement the Recursive Least Squares (QR) algorithm in FPGA.
[Použití logaritmické aritmetiky pro implementaci výpočtu rekurzivních nejmenších čtverců v FPGA obvodu.]
Field-Programmable Logic and Applications. 14th International Conference FPL 2004. Proceedings. Berlin: Springer, 2004 - (Becker, J.; Platzner, M.; Vernalde, S.), s. 1149-1151. Lecture Notes in Computer Science., 3203. ISBN 3-540-22989-2.
[International Conference FPL 2004 /14./. Antverp (BE), 30.08.2004-01.09.2004]
R&D Projects: GA MŠMT LN00B096; GA AV ČR 1ET400750408; GA AV ČR 1ET300750402
Institutional research plan: CEZ:AV0Z1075907
Keywords : QR update * FPGA * logarithmic arithmetic
Subject RIV: BD - Theory of Information
Permanent Link: http://hdl.handle.net/11104/0013508 - 4.0106325 - UTIA-B 20040137 RIV AT eng C - Conference Paper (international conference)
Heřmánek, Antonín - Schier, Jan - Regalia, P.
Architecture design for FPGA implementation of finite interval CMA.
[Návrh architektury pro FPGA implementaci blokového CMA algoritmu (Finite interval CMA).]
Proceedings of the 12th European Signal Processing Conference. Vienna: University of Technology, 2004 - (Hlawatsch, F.; Matz, G.; Rupp, M.), s. 1-4. ISBN 3-200-00165-8.
[EUSIPCO 2004 /12./. Vienna (AT), 06.09.2004-10.09.2004]
R&D Projects: GA MŠMT LN00B096; GA AV ČR 1ET300750402; GA AV ČR 1ET400750408
Institutional research plan: CEZ:AV0Z1075907
Keywords : blind equalization * CMA, FPGA * logarithmic arithmetic
Subject RIV: BD - Theory of Information
Permanent Link: http://hdl.handle.net/11104/0013507 - 5.0075993 - ÚTIA 2007 RIV FR eng C - Conference Paper (international conference)
Šůcha, P. - Hanzálek, Z. - Heřmánek, Antonín - Schier, Jan
Efficient FPGA Implementation of Equalizer for Finite Interval Constant Modulus Algorithm.
[Efektivní FPGA implementace FI-CMA ekvalizéru.]
IEEE Symposium on Industrial Embedded Systems - IES 2006, Proceedings of. Lyon: CNRS-ENS, 2006, s. 1-10. ISBN 1-4244-0777-X.
[IEEE Symposium on Industrial Embedded Systems - IES 2006. Antibes Juan-Les-Pins (FR), 18.10.2006-20.10.2006]
R&D Projects: GA AV ČR(CZ) 1ET300750402; GA AV ČR(CZ) 1ET400750406; GA MŠMT(CZ) 1M0567
Institutional research plan: CEZ:AV0Z10750506
Keywords : high-level synthesis * cyclic scheduling * iterative algorithms * imperfectly nested loops * integer linear programming * FPGA * control
Subject RIV: JA - Electronics ; Optoelectronics, Electrical Engineering
Permanent Link: http://hdl.handle.net/11104/0143207 - 6.0026328 - ÚTIA 2006 RIV FI eng C - Conference Paper (international conference)
Pohl, Zdeněk - Kadlec, Jiří - Šůcha, P. - Hanzálek, Z.
Performance tuning of interative algorithms in signal processing.
[Ladění výkonu iterativních algoritmů pro zpracování signálu.]
Proseedings of the 2005 International Conference on Field Programmable Logic and Applications. FPL 2005. Tampere: Academy of Finland, 2005 - (Rissa, T.; Wilton, S.; Leong, P.), s. 699-702. ISBN 0-7803-9362-7.
[FPL 2005. International Conference on Field Programmable Logic and Applications. Tampere (FI), 24.08.2005-26.08.2005]
R&D Projects: GA AV ČR(CZ) 1ET300750402; GA MŠMT(CZ) 1M0567
Institutional research plan: CEZ:AV0Z10750506
Keywords : signal processing * FPGA * high speed logarithmic arithmetic
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0116596