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Records found: 2  
Your query: Author Sysno/Doc.kind = "^cav_un_auth 0202863 zk^"
    1.
    0411459 - UTIA-B 20050189 CZ eng K - Conference Paper (Czech conference)
    Kafka, Leoš - Matoušek, Rudolf
    Design Retiming in HDL.
    [Design Retiming na HDL úrovni.]
    Praha: ČVUT, 2005. ISBN 80-01-03201-9. In: Proceedings of Workshop 2005. - (Říha, B.), s. 258-259
    [Annual University-Wide Seminar. WORKSHOP 2005 /13./. Praha (CZ), 21.03.2005-25.03.2005]
    R&D Projects: GA ČR 102/04/2137
    Grant - others:Commission EC(BE) IST-2001-34016
    Institutional research plan: CEZ:AV0Z10750506
    Keywords : FPGA * VHDL * Synplify Pro
    Subject RIV: JC - Computer Hardware ; Software
    Permanent Link: http://hdl.handle.net/11104/0131540
     
     
    2.
    0411433 - UTIA-B 20050163 CZ eng K - Conference Paper (Czech conference)
    Kafka, Leoš
    An FPGA-based fault injector for TSC circuits.
    [Injektor poruch pro TSC obvody založený na FPGA.]
    Praha: ČVUT FEL, 2005. ISBN 80-01-03298-1. In: Počítačové architektury a diagnostika. - (Lórencz, R.; Buček, J.; Zahradnický, T.), s. 77-81
    [Počítačové architektury a diagnostika 2005. PAD 2005. Lázně Sedmihorky (CZ), 21.09.2005-23.09.2005]
    R&D Projects: GA MŠMT 1QS108040510
    Institutional research plan: CEZ:AV0Z10750506
    Keywords : fault simulation * concurrent error detection * FPGA
    Subject RIV: JC - Computer Hardware ; Software
    Permanent Link: http://hdl.handle.net/11104/0131514
     
     


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