Search results
- 1.0411372 - UTIA-B 20050102 RIV BE eng C - Conference Paper (international conference)
Bartosinski, Roman - Daněk, Martin - Honzík, Petr - Matoušek, Rudolf
Dynamic reconfiguration in FPGA-based SoC designs.
[Dynamická rekonfigurace v SoC návrhu s obvody FPGA. Dynamická rekonfigurace v SoC návrhu s obvody FPGA.]
Ghent: HiPEAC Network of Excellence, 2005. ISBN 90-382-0802-2. In: ACACES 2005. Advanced Computer Architecture and Compilation for Embedded Systems. - (Bosschere, K.), s. 35-38
[ACACES 2005. L'Aquila (IT), 26.07.2005]
R&D Projects: GA MŠMT 1M0567
Grant - others:Commission EC(XE) IST-2001-34016
Institutional research plan: CEZ:AV0Z10750506
Keywords : dynamic reconfiguration * FPGA * HW/SW codesign
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0131454 - 2.0411311 - UTIA-B 20050039 RIV HU eng C - Conference Paper (international conference)
Bartosinski, Roman - Daněk, Martin - Honzík, Petr - Matoušek, Rudolf
Dynamic reconfiguration in FPGA-based SoC designs.
[Dynamická rekonfigurace v FPGA systémech na jednom čipu.]
Sopron: University of West Hungary, 2005. ISBN 963-9364-48-7. In: Proceedings of the 8th IEEE Workshop on Designs and Diagnostics of Electronic Circuits nad Systems. - (Takách, G.; Hlawiczka, A.; Sziraj, J.), s. 129-136
[IEEE Design and Diagnostics of Electronic Circuits nad Systems Workshop (DDECS 2005) /8./. Sopron (HU), 13.04.2005-16.04.2005]
R&D Projects: GA MŠMT 1M0567
Grant - others:Commission EC(XE) IST-2001-34016
Institutional research plan: CEZ:AV0Z10750506
Keywords : FPGA * dynamic reconfiguration
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0131394 - 3.0382187 - ÚTIA 2013 RIV FR eng C - Conference Paper (international conference)
Bartosinski, Roman - Daněk, Martin - Sýkora, Jaroslav - Kohout, Lukáš - Honzík, P.
Foreground Detection and Image Segmentation in a Flexible ASVP Platform for FPGAs.
Proceedings of the 2012 Conference on Design & Architectures for Signal & Image Processing. Gières: Electronic Chips & Systems design Initiative, 2012 - (Morawiec, A.; Hinderscheit, J.), s. 375-376. ISBN 978-2-9539987-2-6. ISSN 1966-7116.
[Conference on Design & Architectures for Signal & Image Processing. Karlsruhe (DE), 23.10.2012-25.10.2012]
R&D Projects: GA MŠMT(CZ) 7H10001
Institutional support: RVO:67985556
Keywords : video surveillance * smart camera * custom accelerators * vector processing * FPGA
Subject RIV: JC - Computer Hardware ; Software
http://library.utia.cas.cz/separaty/2012/ZS/bartosinski-0382187.pdf
Permanent Link: http://hdl.handle.net/11104/0212481 - 4.0382184 - ÚTIA 2013 RIV FR eng C - Conference Paper (international conference)
Bartosinski, Roman - Daněk, Martin - Sýkora, Jaroslav - Kohout, Lukáš - Honzík, P.
Video Surveillance Application Based on Application Specific Vector Processors.
Proceedings of the 2012 Conference on Design & Architectures for Signal & Image Processing. Gières: Electronic Chips & Systems design Initiative, 2012 - (Morawiec, A.; Hinderscheit, J.), s. 248-255. ISBN 978-2-9539987-2-6. ISSN 1966-7116.
[Conference on Design & Architectures for Signal & Image Processing. Karlsruhe (DE), 23.10.2012-25.10.2012]
R&D Projects: GA MŠMT(CZ) 7H10001
Institutional support: RVO:67985556
Keywords : video surveillance * smart camera * custom accelerators * vector processing * FPGA
Subject RIV: JC - Computer Hardware ; Software
http://library.utia.cas.cz/separaty/2012/ZS/bartosinski-0382184.pdf
Permanent Link: http://hdl.handle.net/11104/0212479 - 5.0380442 - ÚTIA 2013 RIV TR eng C - Conference Paper (international conference)
Sýkora, Jaroslav - Bartosinski, Roman - Kohout, Lukáš - Daněk, Martin - Honzík, P.
Reducing Instruction Issue Overheads in Application-Specific Vector Processors.
Proceedings of the 15th Euromicro Conference on Digital System Design, DSD 2012. Izmir: Conference Publishing Services, 2012 - (Niar, S.), s. 600-607. ISBN 978-0-7695-4798-5.
[15th Euromicro Conference on Digital System Design. Cesme (TR), 05.09.2012-08.09.2012]
R&D Projects: GA MŠMT(CZ) 7H10001
Grant - others:Commission EU(XE) Artemis JU 100230
Keywords : custom accelerators * vector processing * FPGA * DSP
Subject RIV: JC - Computer Hardware ; Software
http://library.utia.cas.cz/separaty/2012/ZS/sykora-reducing instruction issue overheads in application-specific vector processors.pdf
Permanent Link: http://hdl.handle.net/11104/0211153 - 6.0376595 - ÚTIA 2013 RIV EE eng C - Conference Paper (international conference)
Sýkora, Jaroslav - Kohout, Lukáš - Bartosinski, Roman - Kafka, Leoš - Daněk, Martin - Honzík, P.
The Architecture and the Technology Characterization of an FPGA-based Customizable Application-Specific Vector Processor.
Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Tallinn, ESTONIA: IEEE, 2012 - (Raik, J.; Stopjaková, V.; Jenihhin, M.; Vierhaus, H., T.; Pleskacz, W.; Ubar, R.), s. 62-67. ISBN 978-1-4673-1185-4.
[2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Tallinn (EE), 18.04.2012-20.04.2012]
R&D Projects: GA MŠMT(CZ) 7H10001
Institutional research plan: CEZ:AV0Z10750506
Keywords : custom accelerators * vector processing * FPGA
Subject RIV: JC - Computer Hardware ; Software
http://library.utia.cas.cz/separaty/2012/ZS/sykora-0376595.pdf
Permanent Link: http://hdl.handle.net/11104/0208954 - 7.0363078 - ÚTIA 2012 RIV CZ eng C - Conference Paper (international conference)
Bartosinski, Roman
The LD-RLS algorithm with directional forgetting implemented on a vector-like hardware accelerator.
ICASSP 2011: IEEE International Conference on Acoustics, Speech, and Signal Processing. Praha: IEEE, 2011, s. 1657-1660. ISBN 978-1-4577-0539-7.
[ICASSP 2011: IEEE International Conference on Acoustics, Speech, and Signal Processing. Praha (CZ), 22.05.2011-27.05.2011]
R&D Projects: GA MŠMT(CZ) 7H10001
Grant - others:GA MŠk(CZ) JU100230 Artemis
Institutional research plan: CEZ:AV0Z10750506
Keywords : LDU decomposition * directional forgetting * hardware accelerator
Subject RIV: IN - Informatics, Computer Science
http://library.utia.cas.cz/separaty/2011/ZS/bartosinski-0363078.pdf
Permanent Link: http://hdl.handle.net/11104/0199178 - 8.0313340 - ÚTIA 2009 RIV DE eng C - Conference Paper (international conference)
Daněk, Martin - Philippe, J.-M. - Bartosinski, Roman - Honzík, Petr - Gamrat, Ch.
Self-Adaptive Networked Entities for Building Pervasive Computing Aschitectures.
[Samoadaptivní síťová entita pro stavbu pervasivních počítačových architektur.]
International Conference on Evolvable Systems: From Biology to Harware, 8th International Conference, ICES 2008. Heidelberg: Springer, 2008 - (Hornby, G.; Sekanina, L.; Haddow, P.), s. 94-105. ISBN 978-3-540-85856-0. ISSN 0302-9743.
[International Conference on Evolvable Systems: From Biology to Harware, 8th International Conference, ICES 2008. Praha (CZ), 22.09.2008-24.09.2008]
R&D Projects: GA MŠMT(CZ) 1M0567
EU Projects: European Commission(XE) 027611 - AETHER
Program: FP6
Institutional research plan: CEZ:AV0Z10750506
Keywords : Self-adaptation * FPGA * Simulink
Subject RIV: BD - Theory of Information
http://library.utia.cas.cz/separaty/2008/ZS/danek-self-adaptive networked entities for building pervasive computing aschitectures.pdf
Permanent Link: http://hdl.handle.net/11104/0164192 - 9.0313274 - ÚTIA 2009 RIV DE eng C - Conference Paper (international conference)
Daněk, Martin - Kadlec, Jiří - Bartosinski, Roman - Kohout, Lukáš
Increasing the Level of Abstraction in FPGA-based Designes.
[Zvyšování úrovně abstrakce v návrzích založených na FPGA.]
International Conference on Field Programmable Logic and Applications. Heidelberg: Kirchhoff Institute for Physics, 2008 - (Kebschull, U.), s. 5-10. ISBN 978-1-4244-1961-6.
[International Conference on Field Programmable Logic and Applications. Heidelberg (DE), 08.09.2008-10.09.2008]
EU Projects: European Commission(XE) 027611 - AETHER
Program: FP6
Institutional research plan: CEZ:AV0Z10750506
Keywords : FPGA * dataflow * floating-point
Subject RIV: JC - Computer Hardware ; Software
http://library.utia.cas.cz/separaty/2008/ZS/danek-increasing%20the%20level%20of%20abstraction%20in%20fpga-based%20designes.pdf
Permanent Link: http://hdl.handle.net/11104/0164145 - 10.0089564 - ÚTIA 2008 RIV US eng C - Conference Paper (international conference)
Bartosinski, Roman - Hanzálek, Z. - Stružka, P. - Waszniowski, L.
Integrated Environment for Embedded Control Systems Design.
[integrované zařízení pro vložený kontrolní systém nákresu.]
Proceedings of the 21st IEEE International Parallel & Distributed Processing Symposium. Los Alamitos, CA: IEEE Computer Society, 2007, s. 1-8. ISBN 1-4244-0909-8.
[21st IEEE International Parallel & Distributed Processing Symposium. Long Beach (US), 26.03.2007-30.03.2007]
R&D Projects: GA AV ČR 1ET400750406
Institutional research plan: CEZ:AV0Z10750506
Keywords : Code generation * Model based design * Processor Expert * Simulink
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0150738