Search results
- 1.0410837 - UTIA-B 20020051 RIV GB eng J - Journal Article
Kadlec, Jiří - Matoušek, Rudolf - Heřmánek, Antonín - Líčko, Miroslav - Tichý, Milan
Lattice for FPGAs using logarithmic arithmetic.
Electronic Engineering. Roč. 74, č. 906 (2002), s. 53-56. ISSN 0013-4902
Grant - others:ESPRIT(XE) 33544
Institutional research plan: CEZ:AV0Z1075907
Keywords : lattice Rls algorithm * FPGA * logarithmic arithmetic
Subject RIV: JC - Computer Hardware ; Software
Impact factor: 0.039, year: 2002
Permanent Link: http://hdl.handle.net/11104/0130924 - 2.0410576 - UTIA-B 20010045 RIV SK eng J - Journal Article
Tichý, Milan - Zemánek, P.
Performance and tuning of the UNIX operating system.
Journal of Electrical Engineering - Elektrotechnický časopis. 3/4 (2001), s. 74-80. ISSN 1335-3632. E-ISSN 1339-309X
Institutional research plan: AV0Z1075907
Keywords : operating system * process * file system
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0130665 - 3.0341115 - ÚTIA 2011 RIV US eng J - Journal Article
Tichý, Milan - Schier, Jan - Gregg, D.
GSFAP Adaptive Filtering Using Log Arithmetic for Resource-Constrained Embedded Systems.
ACM Transactions on Embedded Computing Systems. Roč. 9, č. 3 (2010), s. 1-31. ISSN 1539-9087. E-ISSN 1558-3465
R&D Projects: GA MŠMT 7H09005
Institutional research plan: CEZ:AV0Z10750506
Keywords : FPGA * DSP * logarithmic arithmetic * affine projection
Subject RIV: BD - Theory of Information
Impact factor: 1.057, year: 2010
http://library.utia.cas.cz/separaty/2010/ZS/tichy-0341115.pdf
Permanent Link: http://hdl.handle.net/11104/0184199 - 4.0312228 - ÚTIA 2009 RIV US eng J - Journal Article
Pohl, Zdeněk - Tichý, Milan - Kadlec, Jiří
Implementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA.
[Implementace příčkového algoritmu nejmenších čtverců s odhadem řádu a zapomínaní pro FPGA.]
EURASIP Journal on Advances in Signal Processing. Roč. 2008, č. 2008 (2008), s. 1-11. ISSN 1687-6172
R&D Projects: GA MŠMT(CZ) 1M0567
EU Projects: European Commission(XE) 027611 - AETHER
Program: FP6
Institutional research plan: CEZ:AV0Z10750506
Keywords : DSP * Least-squares lattice * order estimation * exponential forgetting factor estimation * FPGA implementation * scheduling * dynamic reconfiguration * microblaze
Subject RIV: IN - Informatics, Computer Science
Impact factor: 1.055, year: 2008
http://library.utia.cas.cz/separaty/2008/ZS/pohl-tichy-kadlec-implementation%20of%20the%20least-squares%20lattice%20with%20order%20and%20forgetting%20factor%20estimation%20for%20fpga.pdf
Permanent Link: http://hdl.handle.net/11104/0163345 - 5.0085961 - ÚTIA 2008 RIV US eng J - Journal Article
Coleman, J. N. - Softley, C. I. - Kadlec, Jiří - Matoušek, R. - Tichý, Milan - Pohl, Zdeněk - Heřmánek, Antonín - Benschop, N. F.
The European Logarithmic Microprocessor.
[Evropský logaritmický mikroprocesor.]
IEEE Transactions on Computers. Roč. 57, č. 4 (2008), s. 532-546. ISSN 0018-9340. E-ISSN 1557-9956
Grant - others:Evropská komise(BE) ESPRIT 33544
Institutional research plan: CEZ:AV0Z10750506
Source of funding: R - Framework programmes of European Commission
Keywords : Processor architecture * arithmetic unit * logarithmic arithmetic
Subject RIV: JC - Computer Hardware ; Software
Impact factor: 2.611, year: 2008
http://library.utia.cas.cz/separaty/2008/ZS/kadlec-the%20european%20logarithmic%20microprocessor.pdf
Permanent Link: http://hdl.handle.net/11104/0148357