Search results
- 1.0411315 - UTIA-B 20050043 CZ eng V - Research Report
Šůcha, P. - Heřmánek, Antonín - Schier, Jan - Hanzálek, Z.
Optimization of Finite Interval CMA Implementation for FPGA.
Praha: ÚTIA AV ČR, 2005. 16 s. Research Report, 2127.
R&D Projects: GA MŠMT 1M0567; GA AV ČR 1ET300750402
Institutional research plan: CEZ:AV0Z10750506
Keywords : FPGA * finite interval constant modulus algorithm
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0131398 - 2.0411001 - UTIA-B 20020215 CZ eng V - Research Report
Líčko, Miroslav - Schier, Jan - Pohl, Zdeněk - Kadlec, Jiří - Tichý, Milan - Matoušek, Rudolf - Heřmánek, Antonín
Logarithmic Arithmetic for Real Data Types and Support for MATLAB/SIMULINK Based Rapid-FPGA-Prototyping.
Praha: ÚTIA AV ČR, 2002. 7 s. Research Report, 2069.
R&D Projects: GA MŠMT LN00B096
Institutional research plan: CEZ:AV0Z1075907
Keywords : rapid prototyping for FPGA * MATLAB/Simulink
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0131088 - 3.0410739 - UTIA-B 20010208 CZ eng V - Research Report
Kadlec, Jiří - Albu, F. - Softley, Ch. - Matoušek, Rudolf - Heřmánek, Antonín
RLS Lattice for Virtex FPGA using 32-bit and 20-bit Logarithmic Arithmetic.
Praha: ÚTIA AV ČR, 2001. 11 s. Research Report, 2036.
R&D Projects: GA MŠMT LN00B096
Grant - others:ESPRIT(XE) HSLA 33544
Institutional research plan: AV0Z1075907
Keywords : digital signal processing * logaritmic arithmetic * embedded compilation
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0130827 - 4.0410738 - UTIA-B 20010207 CZ eng V - Research Report
Kadlec, Jiří - Heřmánek, Antonín - Softley, Ch. - Matoušek, Rudolf - Líčko, Miroslav
32-bit Logarithmic ALU for Handel-C 2.1 and Celoxica DK1.
Praha: ÚTIA AV ČR, 2001. 12 s. Research Report, 2037.
R&D Projects: GA MŠMT LN00B096
Grant - others:ESPRIT(XE) HSLA 33544
Institutional research plan: AV0Z1075907
Keywords : field programmable logarithmic array * digital signal processing
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0130826 - 5.0410737 - UTIA-B 20010206 CZ eng V - Research Report
Heřmánek, Antonín - Kadlec, Jiří - Matoušek, Rudolf - Líčko, Miroslav - Softley, Ch.
Pipelined Logarithmic 32bit ALU for Celoxica DK1.
Praha: ÚTIA AV ČR, 2001. 11 s. Research Report, 2034.
R&D Projects: GA MŠMT LN00B096
Grant - others:ESPRIT(XE) HSLA 33544
Institutional research plan: AV0Z1075907
Keywords : FPGA * embedded computer * hardware compilation
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0130825 - 6.0410736 - UTIA-B 20010205 CZ eng V - Research Report
Coleman, J. N. - Kadlec, Jiří - Matoušek, Rudolf - Pohl, Zdeněk - Heřmánek, Antonín
The European Logarithmic Microprocessor - a QRD RLS Applications.
Praha: ÚTIA AV ČR, 2001. 9 s. Research Report, 2038.
R&D Projects: GA MŠMT LN00B096
Grant - others:ESPRIT(XE) HSLA 33544
Institutional research plan: AV0Z1075907
Keywords : logarithmic number system * digital signal processing
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0130824 - 7.0410735 - UTIA-B 20010204 CZ eng V - Research Report
Albu, F. - Kadlec, Jiří - Matoušek, Rudolf - Heřmánek, Antonín - Coleman, J. N.
A Comparison of FPGA Implementation of the A Priori Error-Feedback LSL Algorithm using Logarithmic Arithmetic.
Praha: ÚTIA AV ČR, 2001. 5 s. Research Report, 2035.
R&D Projects: GA MŠMT LN00B096
Grant - others:ESPRIT(XE) HSLA 33544
Institutional research plan: AV0Z1075907
Keywords : LSL Algorithm * FPGA * digital signal processing
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0130823 - 8.0410730 - UTIA-B 20010199 CZ eng V - Research Report
Matoušek, Rudolf - Líčko, Miroslav - Heřmánek, Antonín - Softley, Ch.
Floating-Point-Like Arithmetic for FPGA.
Praha: ÚTIA AV ČR, 2001. 7 s. Research Report, 2039.
R&D Projects: GA MŠMT LN00B096
Grant - others:ESPRIT(XE) HSLA 33544
Institutional research plan: AV0Z1075907
Keywords : floating point * FPGA * digital signal processing
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0130818 - 9.0410729 - UTIA-B 20010198 CZ eng V - Research Report
Albu, F. - Kadlec, Jiří - Softley, Ch. - Matoušek, Rudolf - Heřmánek, Antonín
Implementation of Normalized RLS Lattice on Virtex.
Praha: ÚTIA AV ČR, 2001. 10 s. Research Report, 2040.
R&D Projects: GA MŠMT LN00B096
Grant - others:ESPRIT(XE) HSLA 33544
Institutional research plan: AV0Z1075907
Keywords : digital signal processing * FPGA * floating point
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0130817 - 10.0106372 - UTIA-B 20040184 CZ eng V - Research Report
Pohl, Zdeněk - Heřmánek, Antonín
ADPCM IP Cores.
Praha: ÚTIA AV ČR, 2004. 4 s. Research Report, 2109.
R&D Projects: GA MŠMT LN00B096
Grant - others:RECONF2(XE) IST-2001-34016
Institutional research plan: CEZ:AV0Z1075907
Keywords : FPGA * dynamic reconfiguration * embedded HW
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0013554