Search results
- 1.0410837 - UTIA-B 20020051 RIV GB eng J - Journal Article
Kadlec, Jiří - Matoušek, Rudolf - Heřmánek, Antonín - Líčko, Miroslav - Tichý, Milan
Lattice for FPGAs using logarithmic arithmetic.
Electronic Engineering. Roč. 74, č. 906 (2002), s. 53-56. ISSN 0013-4902
Grant - others:ESPRIT(XE) 33544
Institutional research plan: CEZ:AV0Z1075907
Keywords : lattice Rls algorithm * FPGA * logarithmic arithmetic
Subject RIV: JC - Computer Hardware ; Software
Impact factor: 0.039, year: 2002
Permanent Link: http://hdl.handle.net/11104/0130924 - 2.0085961 - ÚTIA 2008 RIV US eng J - Journal Article
Coleman, J. N. - Softley, C. I. - Kadlec, Jiří - Matoušek, R. - Tichý, Milan - Pohl, Zdeněk - Heřmánek, Antonín - Benschop, N. F.
The European Logarithmic Microprocessor.
[Evropský logaritmický mikroprocesor.]
IEEE Transactions on Computers. Roč. 57, č. 4 (2008), s. 532-546. ISSN 0018-9340. E-ISSN 1557-9956
Grant - others:Evropská komise(BE) ESPRIT 33544
Institutional research plan: CEZ:AV0Z10750506
Source of funding: R - Framework programmes of European Commission
Keywords : Processor architecture * arithmetic unit * logarithmic arithmetic
Subject RIV: JC - Computer Hardware ; Software
Impact factor: 2.611, year: 2008
http://library.utia.cas.cz/separaty/2008/ZS/kadlec-the%20european%20logarithmic%20microprocessor.pdf
Permanent Link: http://hdl.handle.net/11104/0148357 - 3.0075925 - ÚTIA 2007 RIV NL eng J - Journal Article
Šůcha, P. - Hanzálek, Z. - Heřmánek, Antonín - Schier, Jan
Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design—Implementation of Finite Interval Constant Modulus Algorithm.
[Rozvrhování iterativních algoritmů s maticovými operacemi pro efektivní FPGA návrh - Implementace Finite interval Constant Modulus algoritmu.]
Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology. Roč. 46, č. 1 (2007), s. 35-53. ISSN 0922-5773
R&D Projects: GA AV ČR(CZ) 1ET300750402; GA MŠMT(CZ) 1M0567; GA MPO(CZ) FD-K3/082
Institutional research plan: CEZ:AV0Z10750506
Keywords : high-level synthesis * cyclic scheduling * iterative algorithms * imperfectly nested loops * integer linear programming * FPGA * VLSI design * blind equalization * implementation
Subject RIV: BA - General Mathematics
Impact factor: 0.449, year: 2007
http://www.springerlink.com/content/t217kg0822538014/fulltext.pdf
Permanent Link: http://hdl.handle.net/11104/0143157