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- 1.0081306 - ÚTIA 2007 RIV CZ cze E - Electronic Document
Heřmánek, Antonín - Dušek, J. - Kloub, Jan
Demonstrátor Reed-Solomonova kodéru a dekodéru s ethernetovým rozhraním implentovaný v FPGA.
[FPGA implementation of demonstrator of Reed-Solomon encoder and decoder with ethernet interface.]
[program]. - Praha: ÚTIA AV ČR, 2007, 16,5 MB
R&D Projects: GA AV ČR 1ET100750408
Institutional research plan: CEZ:AV0Z10750506
Keywords : FPGA * Reed-Solomon encoder * Reed-Solomon decoder * PicoBlaze processor
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0145221 - 2.0079829 - ÚTIA 2007 RIV CZ cze E - Electronic Document
Mazanec, Tomáš - Heřmánek, Antonín
Simulátor fyzické vrstvy ADSL modemu.
[Simulator of physical layer of ADSL modem.]
[program]. - Praha: ÚTIA AV ČR, 2007, 1,12 MB
R&D Projects: GA AV ČR 1ET300750402
Institutional research plan: CEZ:AV0Z10750506
Keywords : ADSL * simulation * signal processing
Subject RIV: BC - Control Systems Theory
Permanent Link: http://hdl.handle.net/11104/0144376 - 3.0079768 - ÚTIA 2007 RIV CZ cze E - Electronic Document
Heřmánek, Antonín - Dušek, J.
Reed Solomonův kodér a dekodér pro FPGA.
[Reed Solomon coder and decoder for FPGA.]
[program]. - Praha: ÚTIA AV ČR, 2007, 12,8 MB
R&D Projects: GA AV ČR 1ET100750408
Institutional research plan: CEZ:AV0Z10750506
Keywords : FPGA * RS coder * Handel C
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0144339 - 4.0079564 - ÚTIA 2007 RIV CZ cze E - Electronic Document
Mazanec, Tomáš - Heřmánek, Antonín
Simulace ADSL downstream přenosu Webová aplikace.
[Simulation of ADSL downstream data transmitting (Web application).]
[program]. - Praha: ÚTIA AV ČR, 2007, 764 kB
R&D Projects: GA AV ČR 1ET300750402
Institutional research plan: CEZ:AV0Z10750506
Keywords : ADSL * TEQ
Subject RIV: BC - Control Systems Theory
Permanent Link: http://hdl.handle.net/11104/0144231 - 5.0079563 - ÚTIA 2007 RIV CZ cze E - Electronic Document
Kvasnička, M. - Heřmánek, Antonín - Kuneš, Michal
Implementace akcelerátoru pro výpočet pro výpočet věrohodnostní funkce.
[Implementation of accelerator for computation of the cross ambiguity function (CAF).]
[program]. - Praha: ÚTIA AV ČR, 2007, 10,4 MB
R&D Projects: GA MŠMT(CZ) 1M0567
Institutional research plan: CEZ:AV0Z10750506
Keywords : FPGA * CAF * PCL systems
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0144230