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0316662 - ÚTIA 2009 RIV US eng C - Conference Paper (international conference)
Šůcha, P. - Pohl, Zdeněk - Hanzálek, Zdeněk
Scheduling of iterative algorithms on FPGA with pipelined arithmetic unit.
[Rozvrhování iterativních algoritmů pro zřetězené aritmetické jednotky na FPGA.]
Real-Time and Embedded Technology and Applications Symposium. Washington DC: IEEE Computer Society, 2004, s. 404-412. ISBN 0-7695-2148-7.
[IEEE Real-Time and Embedded Technology and Applications Symposium 2004 /10./. Toronto (CA), 25.05.2004-28.05.2004]
R&D Projects: GA MŠMT(CZ) LN00B096
Institutional research plan: CEZ:AV0Z1075907
Keywords : cyclic scheduling * monoprocessor * iterative algorithms * integer linear programming * FPGA
Subject RIV: IN - Informatics, Computer Science
http://library.utia.cas.cz/separaty/2008/ZS/pohl-scheduling of iterative algorithms on fpga with pipelined arithmetic unit.pdf
Permanent Link: http://hdl.handle.net/11104/0166512