Search results
- 1.0411362 - UTIA-B 20050092 RIV US eng J - Journal Article
Matoušek, Rudolf - Daněk, Martin - Pohl, Zdeněk - Bartosinski, Roman - Honzík, Petr
Reconfigurable System-on-a-Chip.
[Rekonfigurovatelné systémy na jediném čipu.]
Syndicated. Roč. 5, č. 2 (2005), s. 1-3
R&D Projects: GA AV ČR 1ET400750406; GA AV ČR 1QS108040510; GA AV ČR 1ET400750408
Institutional research plan: CEZ:AV0Z10750506
Keywords : FPGA * dynamic reconfiguratio * system-on-chip
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0131444 - 2.0411292 - UTIA-B 20050020 RIV US eng J - Journal Article
Daněk, Martin - Honzík, Petr - Kadlec, Jiří - Matoušek, Rudolf - Pohl, Zdeněk
Reconfigurable system on programmable chip platform.
[Rekonfigurovatelný systém pro programovatelný integrovaný obvod.]
ATMEL Applications Journal. č. 4 (2005), s. 9-12
R&D Projects: GA ČR GA102/04/2137
Grant - others:EU FP5 IST Programme(XE) IST-2001-34016
Institutional research plan: CEZ:AV0Z10750506
Keywords : reconfigurable system * FPGA
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0131375 - 3.0380861 - ÚTIA 2013 RIV RO eng J - Journal Article
Daněk, Martin - Kafka, Leoš - Kohout, Lukáš - Sýkora, Jaroslav
Hardware Support for Fine-Grain Multi-Threading in LEON3.
Carpathian Journal of Electronic and Computer Engineering. Roč. 4, č. 1 (2011), s. 27-34. ISSN 1844-9689
R&D Projects: GA MŠMT 7E08013
Grant - others:European Commission(BE) FP7-ICT-215216
Keywords : multithreading * microthreading * SPARC * microarchitecture * FPGA
Subject RIV: JC - Computer Hardware ; Software
http://library.utia.cas.cz/separaty/2011/ZS/danek-0380861.pdf
Permanent Link: http://hdl.handle.net/11104/0211467 - 4.0045101 - ÚTIA 2007 RIV CZ cze J - Journal Article
Matoušek, Rudolf - Daněk, Martin - Kubátová, H.
Perspektivy dynamické rekonfigurace programovatelných polí FPGA.
[Prospects of Dynamic Reconfiguration of Field-Programmable Gate Arrays.]
Sdělovací technika. Roč. 54, č. 4 (2006), s. 3-6. ISSN 0036-9942
R&D Projects: GA ČR GA102/04/2137
Grant - others:Evropská komise(BE) IST-2001-34016
Institutional research plan: CEZ:AV0Z10750506
Keywords : FPGA * dynamic reconfiguration * digital design
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0137736 - 5.0040187 - ÚTIA 2007 RIV CZ cze J - Journal Article
Daněk, Martin
Programovatelná hradlová pole - FPGA.
[Field-Programmable gate Arrays.]
Automa. Roč. 12, č. 2 (2006), s. 9-13. ISSN 1210-9592
R&D Projects: GA ČR GA102/04/2137
Institutional research plan: CEZ:AV0Z10750506
Keywords : FPGA architecture * physical design * design flow
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0133995 - 6.0039044 - ÚTIA 2007 RIV CZ cze J - Journal Article
Daněk, Martin - Honzík, Petr - Kadlec, Jiří - Pohl, Zdeněk - Matoušek, Rudolf
Platforma s částečnou dynamickou rekonfigurací FPGA.
[Reconfigurable System-on-a-Programable-Chip Platform.]
Automa. Roč. 12, č. 5 (2006), s. 40-43. ISSN 1210-9592
R&D Projects: GA ČR GA102/04/2137
Grant - others:Commisions EC(XE) IST-2001-34016
Institutional research plan: CEZ:AV0Z10750506
Keywords : FPGA * dynamic reconfiguration * SoC
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0133224