Search results
- 1.0411301 - UTIA-B 20050029 US eng A - Abstract
Nasi, K. - Daněk, Martin - Karoubalis, T. - Pohl, Zdeněk
Figaro: An automatic tool flow for designs with dynamic reconfiguration. Abstract.
[Figaro: Nástroj pro automatické sestavování návrhů s dynamickou rekonfigurací. Abstrakt.]
Monterey: ACM, 2005. ISBN 1-59593-029-9. FPGA 2005 - ACM/SIGDA Thirteenth ACM International Symposium on Field-Programmable Gate Arrays. - (Schmidt, H.; Wilton, S.). s. 262
[FPGA 2005 /13./. 20.02.2005-22.02.2005, Monterey]
R&D Projects: GA ČR GA102/04/2137
Grant - others:IST FP5(XE) IST-2001-34016
Institutional research plan: CEZ:AV0Z10750506
Keywords : FPGA modelling * timing-driven design * placement
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0131384 - 2.0411299 - UTIA-B 20050027 US eng A - Abstract
Bartosinski, Roman - Daněk, Martin - Honzík, Petr - Matoušek, Rudolf
Dynamic reconfiguration in FPGA-based SoC designs. Abstract.
[Dynamická rekonfigurace v SoC návrzích založených na FPGA obvodech. Abstrakt.]
Monterey: ACM, 2005. ISBN 1-59593-029-9. FPGA 2005 - ACM/SIGDA Thirteenth ACM International Symposium on Field-Programmable Gate Arrays. - (Schmidt, H.; Wilton, S.). s. 274
[FPGA 2005 /13./. 20.02.2005-22.02.2005, Monterey]
R&D Projects: GA ČR GA102/04/2137
Grant - others:IST FP5(XE) IST-2001-34016
Institutional research plan: CEZ:AV0Z10750506
Keywords : dynamic reconfiguration * FPGA * HW/SW codesign
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0131382 - 3.0106220 - UTIA-B 20040030 US eng A - Abstract
Daněk, Martin - Kolář, J.
FPGA modelling for high-performance algorithms. Abstract.
FPGA 2004 ACM/SIGDA Twelfth International Symposium on Field-Programmable Gate Arrays. Monterey: ACM, 2004 - (Tessier, R.; Schmidt, H.). s. 251. ISBN 1-58113-829-6.
[FPGA 2004 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays /12./. 22.02.2004-24.02.2004, Monterey]
R&D Projects: GA ČR GA102/04/2137
Institutional research plan: CEZ:AV0Z1075907
Keywords : FPGA * timing-driven algorithms
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0013402