Search results
- 1.0411313 - UTIA-B 20050041 RIV HU eng C - Conference Paper (international conference)
Kafka, Leoš - Kubalík, P. - Kubátová, H. - Novák, O.
Fault classification for self-checking circuits implemented in FPGA.
[Klasifikace poruch pro samočinně kontrolované obvody.]
Sopron: University of West Hungary, 2005. ISBN 963-9364-48-7. In: Proceedings of the 8th IEEE Workshop on Design and Diagnostics of Electronics Circuits and Systems. - (Takách, G.; Hlawiczka, A.; Sziray, J.), s. 228-231
[IEEE Design and Diagnostics of Electronics Circuits and Systems Workshop /8./. Sopron (HU), 13.04.2005-16.04.2005]
R&D Projects: GA ČR GA102/04/2137
Institutional research plan: CEZ:AV0Z10750506
Keywords : concurrent error detection * FPGA * ED codes
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0131396 - 2.0106234 - UTIA-B 20040045 RIV SK eng C - Conference Paper (international conference)
Daněk, Martin - Honzík, Petr - Kadlec, Jiří - Matoušek, Rudolf - Pohl, Zdeněk
Reconfigurable system-on-a-programmable-chip platform.
[Rekonfigurovatelná SOPC platforma.]
Proceedings of the 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Bratislava: Institute of Informatics SAS, 2004 - (Peng, Z.; Fischerová, M.; Gramatová, E.), s. 21-28. ISBN 80-969117-9-1.
[IEEE Workshop on DDECS 2004 /7./. Stará Lesná (SK), 18.04.2004-21.04.2004]
R&D Projects: GA ČR GA102/04/2137
Grant - others:Commission EU(XE) IST-2001-34016
Institutional research plan: CEZ:AV0Z1075907
Keywords : reconfigurable hardware * system-on-chip * methodology
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0013416 - 3.0040204 - ÚTIA 2007 RIV CZ eng C - Conference Paper (international conference)
Kadlec, Jiří - Daněk, Martin
Design and verification methodology for reconfigurable designs in Atmel FPSLIC.
[Metody návrhu a verifikace pro rekonfigurovatelné návrhy v obvodu Atmel FPSLIC.]
Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits adn Systems. Prague: Czech Technical University, 2006 - (Reorda, M.; Novák, O.; Straube, B.), s. 79-80. ISBN 1-4244-0184-4.
[DDECS 2006. IEEE Design and Diagnostics of Electronic Circuits and Systems. Prague (CZ), 18.04.2006-21.04.2006]
R&D Projects: GA ČR GA102/04/2137
EU Projects: European Commission(XE) 027611 - AETHER
Grant - others:Commission EC(XE) IST-2001-34016
Program: FP6
Institutional research plan: CEZ:AV0Z10750506
Keywords : FPGA * dynamic reconfiguration * FPSLIC * floating-point IP cores * design flow
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0134004 - 4.0026311 - ÚTIA 2006 RIV FI eng C - Conference Paper (international conference)
Daněk, Martin - Pohl, Zdeněk - Nasi, K. - Karoubalis, T.
Figaro - an automatic tool flow for designs with dynamic reconfiguration.
[Figaro - automatický nástroj pro návrhy s dynamickou rekonfigurací.]
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications. FPL 2005. Tampere: Academy of Finland, 2005 - (Rissa, T.; Wilton, S.; Leong, P.), s. 590-593. ISBN 0-7803-9362-7.
[FPL 2005. International Conference on Field Programmable Logic and Applications. Tampere (FI), 22.08.2006-26.08.2005]
R&D Projects: GA ČR(CZ) GA102/04/2137
Grant - others:Commission EC(XE) IST-200134016
Institutional research plan: CEZ:AV0Z10750506
Keywords : dynamic reconfiguration * FPGA * Figaro
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0116582