Search results
- 1.0089564 - ÚTIA 2008 RIV US eng C - Conference Paper (international conference)
Bartosinski, Roman - Hanzálek, Z. - Stružka, P. - Waszniowski, L.
Integrated Environment for Embedded Control Systems Design.
[integrované zařízení pro vložený kontrolní systém nákresu.]
Proceedings of the 21st IEEE International Parallel & Distributed Processing Symposium. Los Alamitos, CA: IEEE Computer Society, 2007, s. 1-8. ISBN 1-4244-0909-8.
[21st IEEE International Parallel & Distributed Processing Symposium. Long Beach (US), 26.03.2007-30.03.2007]
R&D Projects: GA AV ČR 1ET400750406
Institutional research plan: CEZ:AV0Z10750506
Keywords : Code generation * Model based design * Processor Expert * Simulink
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0150738 - 2.0089531 - ÚTIA 2008 RIV US eng C - Conference Paper (international conference)
Bartosinski, Roman - Hanzálek, Z. - Waszniowski, L. - Stružka, P.
Processor Expert Enhances Matlab Simulink Facilities for Embedded Software Rapid Development.
[Zpracovatel odborného zvýšení Matlab Simulinkové možnosti pro vložený software rychlého vývoje.]
Emerging Technologies and Factory Automation 2006. Piscataway: IEEE, 2006, s. 1-4. ISBN 0-7803-9758-4.
[IEEE Conference on Emerging Technologies and Factory Automation 2006. Prague (CZ), 20.09.2006-22.09.2006]
R&D Projects: GA AV ČR 1ET400750406
Institutional research plan: CEZ:AV0Z10750506
Keywords : Code generation * Model based design * Processor Expert * Simulink
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0150718 - 3.0085964 - ÚTIA 2010 RIV NL eng C - Conference Paper (international conference)
Kadlec, Jiří - Bartosinski, Roman - Daněk, Martin
Accelerating MicroBlaze Floating Point Operations.
[Akcelerace operací v pohyblivé čárce pro MicroBlaze.]
Proceedings 2007 International Conference on Field Programmable Logic and Applications (FPL). Delft: IEEE, 2007 - (Bertels, K.; Najjar, W.; Genderen, A.; Vassiliadis, S.), s. 621-624. ISBN 978-1-4244-1059-0; ISBN 1-4244-1060-6.
[International Conference on Field Programmable Logic and Applications. FPL 2007. Amsterdam (NL), 27.08.2007-29.08.2007]
R&D Projects: GA AV ČR 1ET400750406; GA MŠMT(CZ) 1M0567
EU Projects: European Commission(XE) 027611 - AETHER
Program: FP6
Institutional research plan: CEZ:AV0Z10750506
Keywords : acceleration * floating point operation * coprocessor * MicroBlaze
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0004136 - 4.0075993 - ÚTIA 2007 RIV FR eng C - Conference Paper (international conference)
Šůcha, P. - Hanzálek, Z. - Heřmánek, Antonín - Schier, Jan
Efficient FPGA Implementation of Equalizer for Finite Interval Constant Modulus Algorithm.
[Efektivní FPGA implementace FI-CMA ekvalizéru.]
IEEE Symposium on Industrial Embedded Systems - IES 2006, Proceedings of. Lyon: CNRS-ENS, 2006, s. 1-10. ISBN 1-4244-0777-X.
[IEEE Symposium on Industrial Embedded Systems - IES 2006. Antibes Juan-Les-Pins (FR), 18.10.2006-20.10.2006]
R&D Projects: GA AV ČR(CZ) 1ET300750402; GA AV ČR(CZ) 1ET400750406; GA MŠMT(CZ) 1M0567
Institutional research plan: CEZ:AV0Z10750506
Keywords : high-level synthesis * cyclic scheduling * iterative algorithms * imperfectly nested loops * integer linear programming * FPGA * control
Subject RIV: JA - Electronics ; Optoelectronics, Electrical Engineering
Permanent Link: http://hdl.handle.net/11104/0143207 - 5.0026139 - ÚTIA 2006 RIV US eng C - Conference Paper (international conference)
Kadlec, Jiří - Gook, R.
Floating point controller as a picoblaze network on a single spartan 3 FPGA.
[adič pro výpočty v pohyblivé řádové čárce pomocí sítě procesorů v FPGA obvodu Spartan3.]
MAPLD 2005 International Conference Proceeding. Washington: NASA Office of Logic Design, 2005 - (Katz, R.), s. 1-11
[MAPLD 2005 International Conference. Washington (US), 07.09.2005-09.09.2005]
R&D Projects: GA MŠMT(CZ) 1M0567; GA AV ČR(CZ) 1ET400750406
Institutional research plan: CEZ:AV0Z10750506
Keywords : arithmetics * bit-exact modeling precision
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0116432 - 6.0026123 - ÚTIA 2006 RIV CZ eng C - Conference Paper (international conference)
Bartosinski, Roman - Stružka, P. - Waszniowski, L.
Peert-blockset for processor export and matlab/simuling integration.
[PEERT- knihovna pro integraci nástroje Processor Expert s MATLAB/Simulink.]
Technical Computing Prague 2005 : 13th Annual Conference Proceedings. Praha: VŠCHT, 2005 - (Moler, C.; Procházka, A.; Walden, B.), s. 1-8. ISBN 80-7080-577-3.
[MATLAB 05. Technical Computing Prague 2005. Praha (CZ), 15.11.2005]
R&D Projects: GA AV ČR(CZ) 1ET400750406
Institutional research plan: CEZ:AV0Z10750506
Keywords : Processor expert * MATLAB/Simuling * embedded systems
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0116417