Search results
- 1.0410794 - UTIA-B 20020008 RIV US eng C - Conference Paper (international conference)
Matoušek, R. - Pohl, Z. - Kadlec, Jiří - Tichý, Milan - Heřmánek, Antonín
Logarithmic arithmetic core based RLS LATTICE implementation.
Los Alamitos: IEEE, 2002. ISBN 0-7695-1471-5. In: Design, Automation and Test in Europe DATE 02. - (Sciuto, D.; Kloos, C.), s. 271
[Design, Automation and Test in Europe DATE 02. Paris (FR), 04.03.2002-08.03.2002]
R&D Projects: GA MŠMT LN00B096
Institutional research plan: CEZ:AV0Z1075907
Keywords : logaritmic arithmetic core * FPGA * LNS
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0130881 - 2.0410739 - UTIA-B 20010208 CZ eng V - Research Report
Kadlec, Jiří - Albu, F. - Softley, Ch. - Matoušek, Rudolf - Heřmánek, Antonín
RLS Lattice for Virtex FPGA using 32-bit and 20-bit Logarithmic Arithmetic.
Praha: ÚTIA AV ČR, 2001. 11 s. Research Report, 2036.
R&D Projects: GA MŠMT LN00B096
Grant - others:ESPRIT(XE) HSLA 33544
Institutional research plan: AV0Z1075907
Keywords : digital signal processing * logaritmic arithmetic * embedded compilation
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0130827