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Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique
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SYSNO 0346745 Title Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique Author(s) Heřmánek, Antonín (UTIA-B) [ZS]
Kuneš, Michal (UTIA-B) [ZOI] RID
Tichý, Milan (UTIA-B) [ZS]Source Title Proceedings of the International Conference on Field Programmable Logic and Applications. S. 336-339. - Piscataway : IEEE, 2010 Conference 20th International Conference on Field Programmable Logic and Applications, Milano, 31.08.2010-02.09.2010 Document Type Konferenční příspěvek (zahraniční konf.) Grant 7H09005 GA MŠMT - Ministry of Education, Youth and Sports (MEYS) CEZ AV0Z10750506 - UTIA-B (2005-2011) Language eng Country US Keywords FPGA * Clock Gating * Digital design * System on Chip * Multicore Embedded System * Power consumption URL http://library.utia.cas.cz/separaty/2010/ZS/kunes-reducing power consumption of an embedded dsp platform through the clock-gating technique.pdf Permanent Link http://hdl.handle.net/11104/0187684
Number of the records: 1