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Performance of the upgraded preprocessor of the ATLAS Level-1 calorimeter trigger
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SYSNO ASEP 0537666 Document Type J - Journal Article R&D Document Type Journal Article Subsidiary J Článek ve WOS Title Performance of the upgraded preprocessor of the ATLAS Level-1 calorimeter trigger Author(s) Aad, G. (FR)
Abbott, B. (US)
Abbott, D.C. (US)
Chudoba, Jiří (FZU-D) RID, ORCID
Hejbal, Jiří (FZU-D) RID, ORCID
Hladík, Ondřej (FZU-D) ORCID
Jačka, Petr (FZU-D) ORCID
Jakoubek, Tomáš (FZU-D) RID, ORCID
Kepka, Oldřich (FZU-D) RID, ORCID
Kroll, Jiří (FZU-D) ORCID
Kupčo, Alexander (FZU-D) RID, ORCID
Lokajíček, Miloš (FZU-D) RID, ORCID
Lysák, Roman (FZU-D) RID, ORCID
Marčišovský, Michal (FZU-D) RID, ORCID
Mikeštíková, Marcela (FZU-D) RID, ORCID
Němeček, Stanislav (FZU-D) RID, ORCID
Penc, Ondřej (FZU-D) ORCID
Šícho, Petr (FZU-D) RID, ORCID
Staroba, Pavel (FZU-D) RID, ORCID
Svatoš, Michal (FZU-D) RID, ORCID
Taševský, Marek (FZU-D) RID, ORCIDNumber of authors 2897 Article number P11016 Source Title Journal of Instrumentation. - : Institute of Physics Publishing - ISSN 1748-0221
Roč. 15, č. 11 (2020), s. 1-48Number of pages 49 s. Language eng - English Country GB - United Kingdom Keywords ATLAS ; CERN ; LHC ; calorimeters ; FPGA ; trigger Subject RIV BF - Elementary Particles and High Energy Physics OECD category Particles and field physics R&D Projects LM2018104 GA MŠMT - Ministry of Education, Youth and Sports (MEYS) LTT17018 GA MŠMT - Ministry of Education, Youth and Sports (MEYS) Method of publishing Open access Institutional support FZU-D - RVO:68378271 UT WOS 000595650800004 EID SCOPUS 85096705928 DOI 10.1088/1748-0221/15/11/P11016 Annotation The PreProcessor of the ATLAS Level-1 Calorimeter Trigger prepares the analogue trigger signals sent from the ATLAS calorimeters by digitising, synchronising, and calibrating them to reconstruct transverse energy deposits, which are then used in further processing to identify event features. During the first long shutdown of the LHC from 2013 to 2014, the central components of the PreProcessor, the Multichip Modules, were replaced by upgraded versions that feature modern ADC and FPGA technology to ensure optimal performance in the high pile-up environment of LHC Run 2. This paper describes the features of the new Multichip Modules along with the improvements to the signal processing achieved.
Workplace Institute of Physics Contact Kristina Potocká, potocka@fzu.cz, Tel.: 220 318 579 Year of Publishing 2021 Electronic address http://hdl.handle.net/11104/0315526
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