VPart: An automatic partitioning tool for dynamic reconfiguration. Abstract

Kafka, Leoš; Kielbik, R.; Matoušek, Rudolf; Moreno, J. M.

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VPart: An automatic partitioning tool for dynamic reconfiguration. Abstract

1.

SYSNO ASEP	0411302
Document Type	A - Abstract
R&D Document Type	The record was not marked in the RIV
R&D Document Type	Není vybrán druh dokumentu
Title	VPart: An automatic partitioning tool for dynamic reconfiguration. Abstract
Title	VPart: Nástroj pro automatické rozdělení návrhu umožňující dynamickou rekonfiguraci. Abstrakt
Author(s)	Kafka, Leoš (UTIA-B) Kielbik, R. (PL) Matoušek, Rudolf (UTIA-B) Moreno, J. M. (ES)
Year of issue	2005
ISBN	1-59593-029-9
Source Title	FPGA 2005 - ACM/SIGDA Thirteenth International Symposium on Field-Programmable Gate Arrays / Schmidt H. ; Wilton S. s. 263
Number of pages	1 s.
Action	FPGA 2005 /13./
Event date	20.02.2005-22.02.2005
VEvent location	Monterey
Country	US - United States
Event type	WRD
Language	eng - English
Country	US - United States
Keywords	automatic partitioning ; reconfiguration ; design tools
Subject RIV	JC - Computer Hardware ; Software
R&D Projects	LN00B096 GA MŠMT - Ministry of Education, Youth and Sports (MEYS)
CEZ	AV0Z10750506 - UTIA-B (2005-2011)
Annotation	This paper presents an innovative tool for automatic partitioning of VHDL designs for dynamic reconfiguration called VPart. An introduction to the dynamic implementation of a circuit is presented. A design flow and optimization algorithms and methods used by the tool to partition the input design are explained. The usage of the tool is shown on three simple experiments performed on 18-bit floating-point arithmetic adder and multiplier.
Workplace	Institute of Information Theory and Automation
Contact	Markéta Votavová, votavova@utia.cas.cz, Tel.: 266 052 201.
Year of Publishing	2006

Number of the records: 1