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Software Phase Lock Loops Applied in Three-Phase PWM Rectifier
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SYSNO ASEP 0365382 Document Type C - Proceedings Paper (int. conf.) R&D Document Type Conference Paper Title Software Phase Lock Loops Applied in Three-Phase PWM Rectifier Author(s) Šimek, Petr (UT-L) RID
Škramlík, Jiří (UT-L)
Valouch, Viktor (UT-L) RID
Bejvl, Martin (UT-L) RIDSource Title Electrical Drives and Power Electronics - EDPE 11. - Košice : Technical University of Košice, 2011 - ISBN 978-80-553-0734-3 Pages s. 227-232 Number of pages 6 s. Publication form CD ROM - CD ROM Action International Conference on Electrical Drives and Power Electronics - EDPE 11 /17./ Event date 28.10.2011-30.10.2011 VEvent location Stará Lesná, The High Tatras Country SK - Slovakia Event type EUR Language eng - English Country SK - Slovakia Keywords phase lock loop ; unsymmetrical voltage system ; harmonics Subject RIV JA - Electronics ; Optoelectronics, Electrical Engineering R&D Projects FR-TI1/330 GA MPO - Ministry of Industry and Trade (MPO) CEZ AV0Z20570509 - UE-C, UT-L (2005-2011) Annotation Three SPLL (Software Phase Lock Loops)that differ by the method of the detection of symmetrical grid voltage sequences (positive and negative ones) are presented. Simulation and experimental results of these SPLL applied in a three-phase PWM rectifier connected to an unsymmetrical grid voltage system with harmonics are discussed, even under some disturbances and parameter changes of the grid. The function of the DSC (Delayed Signal Cancellation) based SPLL in PWM rectifier with fs = 1600 Hz was experimetally verified under different grid voltage disturbances with satisfactory results. Workplace Institute of Thermomechanics Contact Marie Kajprová, kajprova@it.cas.cz, Tel.: 266 053 154 ; Jana Lahovská, jaja@it.cas.cz, Tel.: 266 053 823 Year of Publishing 2012
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