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Microthreading as a Novel Method for Close Coupling of Custom Hardware Accelerators to SVP Processors

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    SYSNO ASEP0363714
    Document TypeC - Proceedings Paper (int. conf.)
    R&D Document TypeConference Paper
    TitleMicrothreading as a Novel Method for Close Coupling of Custom Hardware Accelerators to SVP Processors
    Author(s) Sýkora, Jaroslav (UTIA-B)
    Kafka, Leoš (UTIA-B)
    Daněk, Martin (UTIA-B)
    Kohout, Lukáš (UTIA-B) RID
    Number of authors4
    Source Title2011 14th Euromicro Conference on Digital System Design Architectures, Methods and Tools DSD 2011. - Oulu, Finsko : IEEE Computer Society Conference Publishing Services, 2011 / Kitsos Paris - ISSN N - ISBN 978-0-7695-4494-6
    Pagess. 525-532
    Number of pages8 s.
    Action14th Euromicro Conference on Digital System Design Architectures, Methods and Tools DSD 2011
    Event date31.08.2011-02.09.2011
    VEvent locationOulu
    CountryFI - Finland
    Event typeWRD
    Languageeng - English
    CountryFI - Finland
    Keywordsmicrothreading ; SVP concurrency model ; UTLEON3 processor
    Subject RIVJC - Computer Hardware ; Software
    R&D Projects7E08013 GA MŠMT - Ministry of Education, Youth and Sports (MEYS)
    CEZAV0Z10750506 - UTIA-B (2005-2011)
    AnnotationWe present a new low-level interfacing scheme for connecting custom accelerators to processors that tolerates latencies that usually occur when accessing hardware accelerators from software. The scheme is based on the Self-adaptive Virtual Processor (SVP) architecture and on the micro-threading concept. Our presentation is based on a sample implementation of the SVP architecture in an extended version of the LEON3 processor called UTLEON3. The SVP concurrency paradigm makes data dependencies explicit in the dynamic tree of threads. This enables a system to execute threads concurrently in different processor cores. Previous SVP work presumed the cores are homogeneous, for example an array of microthreaded processors sharing a dynamic pool of microthreads. In this work we propose a heterogeneous system of general-purpose processor cores and custom hardware accelerators. The accelerators dynamically pick families of threads from the pool and execute them concurrently.
    WorkplaceInstitute of Information Theory and Automation
    ContactMarkéta Votavová, votavova@utia.cas.cz, Tel.: 266 052 201.
    Year of Publishing2012
Number of the records: 1  

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