Number of the records: 1
Analysis of Execution Efficiency in the Microthreaded Processor UTLEON3
- 1.
SYSNO ASEP 0357150 Document Type C - Proceedings Paper (int. conf.) R&D Document Type Conference Paper Title Analysis of Execution Efficiency in the Microthreaded Processor UTLEON3 Author(s) Sýkora, Jaroslav (UTIA-B)
Kafka, Leoš (UTIA-B)
Daněk, Martin (UTIA-B)
Kohout, Lukáš (UTIA-B) RIDSource Title Architecture of Computing Systems - ARCS 2011. - Berlin : Springer-Verlag Berlin Heidelberg, 2011 / Berekovic Mladen - ISSN 0302-9743 - ISBN 978-3-642-19136-7 Pages s. 110-121 Number of pages 12 s. Action ARCS 2011. International Conference on Architecture of computing systems /24./ Event date 24.02.2011-25.02.2011 VEvent location Camo Country IT - Italy Event type WRD Language eng - English Country IT - Italy Keywords Processor architectures ; Multi-threading Subject RIV JC - Computer Hardware ; Software R&D Projects 7E08013 GA MŠMT - Ministry of Education, Youth and Sports (MEYS) CEZ AV0Z10750506 - UTIA-B (2005-2011) UT WOS 000296828800010 EID SCOPUS 79952036320 DOI 10.1007/978-3-642-19137-4_10 Annotation We analyse an impact of long-latency instructions, the family blocksize parameter, and the thread switch modifier on execution efficiency of families of threads in a single-core configuration of the UTLEON3 processor that implements the SVP microthreading model. The analysis is supported by code execution in an FPGA implementation of the processor. The conclusions drawn in this paper can be used to optimize code compilation for the microthreaded processor. As the compiler specifies the blocksize parameter for each family of threads individually, it can optimize the register file utilization of the processor. Workplace Institute of Information Theory and Automation Contact Markéta Votavová, votavova@utia.cas.cz, Tel.: 266 052 201. Year of Publishing 2011
Number of the records: 1