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Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique
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SYSNO ASEP 0346745 Document Type C - Proceedings Paper (int. conf.) R&D Document Type Conference Paper Title Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique Author(s) Heřmánek, Antonín (UTIA-B)
Kuneš, Michal (UTIA-B) RID
Tichý, Milan (UTIA-B)Source Title Proceedings of the International Conference on Field Programmable Logic and Applications. - Piscataway : IEEE, 2010 - ISBN 978-0-7695-4179-2 Pages s. 336-339 Number of pages 4 s. Action 20th International Conference on Field Programmable Logic and Applications Event date 31.08.2010-02.09.2010 VEvent location Milano Country IT - Italy Event type WRD Language eng - English Country US - United States Keywords FPGA ; Clock Gating ; Digital design ; System on Chip ; Multicore Embedded System ; Power consumption Subject RIV JA - Electronics ; Optoelectronics, Electrical Engineering R&D Projects 7H09005 GA MŠMT - Ministry of Education, Youth and Sports (MEYS) CEZ AV0Z10750506 - UTIA-B (2005-2011) Annotation The paper describes application of the clock-gating techniques, often used in ASIC designs, to the field of FPGAbased systems. The clock-gating techniques are used to reduce the total power of the system. To achieve this, we reduce clock power consumption of the system by switching-off the clock signal for the parts of system that are not used. The system presented in this paper is based on the main processor, extended with several reconfigurable accelerators. These accelerators extend the processor capabilities by several vector operations and can be reprogrammed in run-time. Clock gating, in our design, is used to switch the accelerators off when not used. As the accelerators can represent a major part of the system size, switching them off can significantly reduce the power consumption. We also propose the method for estimation of the reduction of power consumption that can be achieved using the clock-gating technique. Workplace Institute of Information Theory and Automation Contact Markéta Votavová, votavova@utia.cas.cz, Tel.: 266 052 201. Year of Publishing 2011
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