Number of the records: 1  

Floating Point Accelerator Families bce_fp01_1x1_0_plbw_v1_|10|20|30|_a bce_fp01_1x2_0_plbw_v1_|10|20|30|40|_a for Xilinx Spartan3 DSP 1800 Board and Petalogix Petalinux-v0.40-final

  1. 1.
    SYSNO ASEP0333688
    Document TypeL - Prototype, Functional Specimen
    R&D Document TypePrototype, Functional Specimen
    RIV SubspeciesPrototype
    TitleFloating Point Accelerator Families bce_fp01_1x1_0_plbw_v1_|10|20|30|_a bce_fp01_1x2_0_plbw_v1_|10|20|30|40|_a for Xilinx Spartan3 DSP 1800 Board and Petalogix Petalinux-v0.40-final
    TitleDemonstrator akcelertorů s aritmetikou v plovoucí řádové čárce bce_fp01_1x1_0_plbw_v1_1|10|20|30_a a bce_fp01_1x2_0_plbw_v1_1|10|20|30|40_a pro Xilinx Spartan3 DSP 1800 a operační systém petalinux-v0.40-final
    Author(s) Kadlec, Jiří (UTIA-B) RID
    Year of issue2009
    Int.Codepočítačová aplikace
    SResult web page, Location of the resultPraha
    Technical parameters1 CD + technická zpráva
    Economic parametersImplementace operačního systému
    Owner NameÚTIA AV ČR
    Registration Number of the result owner67985556
    Applied result category by the cost of its creationA - Vyčerpaná část nákladů <= 5 mil. Kč
    Use by another entityA - Pro využití výsledku jiným subjektem je vždy nutné nabytí licence
    License fee feeA - Poskytovatel licence požaduje licenční poplatek
    Languageeng - English
    CountryCZ - Czech Republic
    KeywordsNonvolatile Field Programable Gate Array ; Embedded uCLinux ; Floating point accelerator
    Subject RIVJC - Computer Hardware ; Software
    R&D Projects1M0567 GA MŠMT - Ministry of Education, Youth and Sports (MEYS)
    CEZAV0Z10750506 - UTIA-B (2005-2011)
    AnnotationThis application note describes parameters and use of an HW demonstrator, designed to demonstrate two floating point accelerator families designed in UTIA. Pre-installed system demonstrates use of four instances of bce_fp01_1x2_|0|1|2|3|_plbw_v1_40_a accelerator on PLB_v46 bus of the Xilinx MicroBlaze soft-core processor on Spartan 3a_dsp FPGA.
    WorkplaceInstitute of Information Theory and Automation
    ContactMarkéta Votavová, votavova@utia.cas.cz, Tel.: 266 052 201.
    Year of Publishing2010
Number of the records: 1  

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