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Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique
- 1.0346745 - ÚTIA 2011 RIV US eng C - Conference Paper (international conference)
Heřmánek, Antonín - Kuneš, Michal - Tichý, Milan
Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique.
Proceedings of the International Conference on Field Programmable Logic and Applications. Piscataway: IEEE, 2010, s. 336-339. ISBN 978-0-7695-4179-2.
[20th International Conference on Field Programmable Logic and Applications. Milano (IT), 31.08.2010-02.09.2010]
R&D Projects: GA MŠMT 7H09005
Institutional research plan: CEZ:AV0Z10750506
Keywords : FPGA * Clock Gating * Digital design * System on Chip * Multicore Embedded System * Power consumption
Subject RIV: JA - Electronics ; Optoelectronics, Electrical Engineering
http://library.utia.cas.cz/separaty/2010/ZS/kunes-reducing power consumption of an embedded dsp platform through the clock-gating technique.pdf
Permanent Link: http://hdl.handle.net/11104/0187684
Number of the records: 1