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Floating Point Accelerator Families bce_fp01_1x1_0_plbw_v1_|10|20|30|_a bce_fp01_1x2_0_plbw_v1_|10|20|30|40|_a for Xilinx Spartan3 DSP 1800 Board and Petalogix Petalinux-v0.40-final

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    0333688 - ÚTIA 2010 RIV CZ eng L - Prototype, f. module
    Kadlec, Jiří
    Floating Point Accelerator Families bce_fp01_1x1_0_plbw_v1_|10|20|30|_a bce_fp01_1x2_0_plbw_v1_|10|20|30|40|_a for Xilinx Spartan3 DSP 1800 Board and Petalogix Petalinux-v0.40-final.
    [Demonstrator akcelertorů s aritmetikou v plovoucí řádové čárce bce_fp01_1x1_0_plbw_v1_1|10|20|30_a a bce_fp01_1x2_0_plbw_v1_1|10|20|30|40_a pro Xilinx Spartan3 DSP 1800 a operační systém petalinux-v0.40-final.]
    Internal code: počítačová aplikace ; 2009
    Technical parameters: 1 CD + technická zpráva
    Economic parameters: Implementace operačního systému
    R&D Projects: GA MŠMT(CZ) 1M0567
    EU Projects: European Commission(XE) 027611 - AETHER
    Program: FP6
    Institutional research plan: CEZ:AV0Z10750506
    Keywords : Nonvolatile Field Programable Gate Array * Embedded uCLinux * Floating point accelerator
    Subject RIV: JC - Computer Hardware ; Software

    This application note describes parameters and use of an HW demonstrator, designed to demonstrate two floating point accelerator families designed in UTIA. Pre-installed system demonstrates use of four instances of bce_fp01_1x2_|0|1|2|3|_plbw_v1_40_a accelerator on PLB_v46 bus of the Xilinx MicroBlaze soft-core processor on Spartan 3a_dsp FPGA.

    Demonstrátor dokladuje parametry a použití dvou rodin akcelerátorů výpočtu v plovoucí řádové čárce na obvodu FPGA 3SD1800a.
    Permanent Link: http://hdl.handle.net/11104/0178620

     
     
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