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Python 1300 Video Sensor Evaluation Platform for TE0720-03-2IF SoM on TE0701-05 Carrier

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    SYSNO ASEP0460676
    Document TypeL - Prototype, Functional Specimen
    R&D Document TypePrototype, Functional Specimen
    RIV SubspeciesFunctional Specimen
    TitlePython 1300 Video Sensor Evaluation Platform for TE0720-03-2IF SoM on TE0701-05 Carrier
    Author(s) Kadlec, Jiří (UTIA-B) RID
    Pohl, Zdeněk (UTIA-B) RID
    Kohout, Lukáš (UTIA-B) RID
    Year of issue2016
    Int.Codet20i2p1
    Technical parametersDemonstrátor umožňuje zpracovávat video signál ze sensoru Python 1300 s rozlišením 1280x1024p60 v obvodu Zynq ZC7020-2I s výstupem na HDMI monitor.
    Economic parametersVstupem je video sensor Python 1300. Barevný video signál je zpracováván pomocí HW akcelerátorů. Je prováděna detekce hran v obraze nebo detekce pohybu. Rozlišení 1280x1024p60, výstup HDMI.
    Owner NameÚstav teorie informace a automatizace AV ČR, v. v. i.
    Registration Number of the result owner67985556
    Applied result category by the cost of its creationA - Vyčerpaná část nákladů <= 5 mil. Kč
    Use by another entityP - Využití výsledku jiným subjektem je v některých případech možné bez nabytí licence
    License fee feeZ - Poskytovatel licence nepožaduje v některých případech licenční poplatek
    Internal identification code of the product assigned by its creator, Regulation no.,http://sp.utia.cz/results/t20i2p1/t20i2p1_2015_4_te0720.pdf
    Languageeng - English
    CountryCZ - Czech Republic
    Keywordsvideo processing accelerator ; FPGA ; video image sensor ; Zynq processing system
    Subject RIVJC - Computer Hardware ; Software
    R&D Projects7H14004 GA MŠMT - Ministry of Education, Youth and Sports (MEYS)
    AnnotationThis application note describes HW platform performing edge detection and motion detection video processing for ON Semi Python 1300 colour video sensor with fixed resolution (1280x1024p60). Arm Cortex A9 processor of Xilinx Zynq is performing initialisation and synchronisation of the video processing chain. Program and the FPGA image is downloaded to the board from the Xilinx SDK 2015.4 via USB JTAG to the 1GB DDR3 located on the Zynq system on module. System can be also started directly from the SD card. Arm processor initiates the IP cores in the programmable logic (PL) part of the Zynq. It also initiates the Python 1300 video sensor and the HDMI video output to monitor with fixed resolution 1280x1024p60.
    WorkplaceInstitute of Information Theory and Automation
    ContactMarkéta Votavová, votavova@utia.cas.cz, Tel.: 266 052 201.
    Year of Publishing2017
    Electronic addresshttp://sp.utia.cz/index.php?ids=results&id=t20i2p1
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