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Dynamic reconfiguration in FPGA-based SoC designs
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SYSNO 0411311 Title Dynamic reconfiguration in FPGA-based SoC designs Title Dynamická rekonfigurace v FPGA systémech na jednom čipu Author(s) Bartosinski, Roman (UTIA-B)
Daněk, Martin (UTIA-B)
Honzík, Petr (UTIA-B)
Matoušek, Rudolf (UTIA-B)Source Title Proceedings of the 8th IEEE Workshop on Designs and Diagnostics of Electronic Circuits nad Systems. s. 129-136 / Takách G. ; Hlawiczka A. ; Sziraj J. Issue data Sopron: University of West Hungary, 2005 ISBN 963-9364-48-7 Conference IEEE Design and Diagnostics of Electronic Circuits nad Systems Workshop (DDECS 2005) /8./, Sopron, 13.04.2005-16.04.2005 Document Type Konferenční příspěvek (zahraniční konf.) Grant IST-2001-34016, XE - EU countries 1M0567 GA MŠMT - Ministry of Education, Youth and Sports (MEYS) CEZ AV0Z10750506 - UTIA-B (2005-2011) Language eng Country HU Keywords FPGA * dynamic reconfiguration Permanent Link http://hdl.handle.net/11104/0131394
Number of the records: 1