Dynamická rekonfigurace v FPGA systémech na jednom čipu
Author(s)
Bartosinski, Roman (UTIA-B) Daněk, Martin (UTIA-B) Honzík, Petr (UTIA-B) Matoušek, Rudolf (UTIA-B)
Issue data
Sopron: University of West Hungary, 2005
ISBN
963-9364-48-7
Source Title
Proceedings of the 8th IEEE Workshop on Designs and Diagnostics of Electronic Circuits nad Systems / Takách G. ; Hlawiczka A. ; Sziraj J.
Pages
s. 129-136
Number of pages
8 s.
Action
IEEE Design and Diagnostics of Electronic Circuits nad Systems Workshop (DDECS 2005) /8./
Event date
13.04.2005-16.04.2005
VEvent location
Sopron
Country
HU - Hungary
Event type
EUR
Language
eng - English
Country
HU - Hungary
Keywords
FPGA ; dynamic reconfiguration
Subject RIV
JC - Computer Hardware ; Software
R&D Projects
1M0567 GA MŠMT - Ministry of Education, Youth and Sports (MEYS)
CEZ
AV0Z10750506 - UTIA-B (2005-2011)
Annotation
This paper discusses architectural issues arising from the use of dynamic reconfiguration and shows a possible use of dynamic reconfiguration to extend and accelerate a computation performed in system-on-a-chip designs with microprocessors with fixed instruction sets. Further a sample application is discussed that uses a dynamically reconfigurable FPGA to implement different floating-point calculations in hardware, reconfigured as required by the execution of the user code.
