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Dynamic reconfiguration in FPGA-based SoC designs
- 1.0411311 - UTIA-B 20050039 RIV HU eng C - Conference Paper (international conference)
Bartosinski, Roman - Daněk, Martin - Honzík, Petr - Matoušek, Rudolf
Dynamic reconfiguration in FPGA-based SoC designs.
[Dynamická rekonfigurace v FPGA systémech na jednom čipu.]
Sopron: University of West Hungary, 2005. ISBN 963-9364-48-7. In: Proceedings of the 8th IEEE Workshop on Designs and Diagnostics of Electronic Circuits nad Systems. - (Takách, G.; Hlawiczka, A.; Sziraj, J.), s. 129-136
[IEEE Design and Diagnostics of Electronic Circuits nad Systems Workshop (DDECS 2005) /8./. Sopron (HU), 13.04.2005-16.04.2005]
R&D Projects: GA MŠMT 1M0567
Grant - others:Commission EC(XE) IST-2001-34016
Institutional research plan: CEZ:AV0Z10750506
Keywords : FPGA * dynamic reconfiguration
Subject RIV: JC - Computer Hardware ; Software
This paper discusses architectural issues arising from the use of dynamic reconfiguration and shows a possible use of dynamic reconfiguration to extend and accelerate a computation performed in system-on-a-chip designs with microprocessors with fixed instruction sets. Further a sample application is discussed that uses a dynamically reconfigurable FPGA to implement different floating-point calculations in hardware, reconfigured as required by the execution of the user code.
Text ukazuje možnosti dynamické rekonfigurace na SoC paltformách založených na FPGA využívajících procesor s pevnou instrukční sadou. Dále je popsán příklad koprocesoru pro FP matematické operace a jeho implementace na dvě komerčně dostupné platformy. Atmel FPSLIC a Xilinx Virtex2. V poslední části je provedeno porovnání obou platforem z několika hledisek vztahujících se k dynamické rekonfiguraci.
Permanent Link: http://hdl.handle.net/11104/0131394
Number of the records: 1