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The LD-RLS algorithm with directional forgetting implemented on a vector-like hardware accelerator
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SYSNO ASEP 0363078 Document Type C - Proceedings Paper (int. conf.) R&D Document Type Conference Paper Title The LD-RLS algorithm with directional forgetting implemented on a vector-like hardware accelerator Author(s) Bartosinski, Roman (UTIA-B) Number of authors 1 Source Title ICASSP 2011: IEEE International Conference on Acoustics, Speech, and Signal Processing. - Praha : IEEE, 2011 - ISBN 978-1-4577-0539-7 Pages s. 1657-1660 Number of pages 4 s. Action ICASSP 2011: IEEE International Conference on Acoustics, Speech, and Signal Processing Event date 22.05.2011-27.05.2011 VEvent location Praha Country CZ - Czech Republic Event type WRD Language eng - English Country CZ - Czech Republic Keywords LDU decomposition ; directional forgetting ; hardware accelerator Subject RIV IN - Informatics, Computer Science R&D Projects 7H10001 GA MŠMT - Ministry of Education, Youth and Sports (MEYS) CEZ AV0Z10750506 - UTIA-B (2005-2011) UT WOS 000296062401223 DOI 10.1109/ICASSP.2011.5946817 Annotation The paper discusses an RLS algorithm based on the LDU decomposition (LD-RLS) with directional forgetting implemented on an embedded system with a vector-oriented hardware accelerator. The LD-RLS algorithm can be attractive for control applications to identify an unknown system or to track time-varying parameters. A solution of the LD-RLS algorithm directly contains the estimated parameters. It also offers a possibility to use a priori information about the identified system and its parameters. The implementation of the LD-RLS algorithm is done on an FPGA-based accelerator from a high-level abstraction. It is compared with an implementation of the same algorithm in software on the same platform. Workplace Institute of Information Theory and Automation Contact Markéta Votavová, votavova@utia.cas.cz, Tel.: 266 052 201. Year of Publishing 2012
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