Number of the records: 1
Analysis of Applicability of Partial Runtime Reconfiguration in Fault Emulator in Xilinx FPGAs
- 1.Kafka, Leoš
Analysis of Applicability of Partial Runtime Reconfiguration in Fault Emulator in Xilinx FPGAs.
Proceedings 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Piscataway: IEEE, 2008 - (Straube, B.; Drutarovský, M.; Renovell, M.; Gramata, P.; Fischerová, M.), s. 178-181. CFP08DDE-PRT. ISBN 978-1-4244-2276-0.
[IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. DDECS 2008 /11./. Bratislava (SK), 16.04.2008-18.04.2008]
R&D Projects: GA AV ČR(CZ) 1QS108040510
http://hdl.handle.net/11104/0159755
Number of the records: 1