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Phase locked loops (PPL) design

  1. 1.
    SYSNO ASEP0303672
    Document TypeC - Proceedings Paper (int. conf.)
    R&D Document TypeConference Paper
    TitlePhase locked loops (PPL) design
    Author(s) Kroupa, Věnceslav František (URE-Y)
    Štursa, Jarmil (URE-Y)
    Issue dataPlzeň: Vydavatelství Západočeské univerzity, 2000
    ISBN80-7082-650-9
    Source TitleAplikovaná elektronika'2000. Sborník referátů mezinárodní konference / Pinker J.
    Pagess. 99-102
    Number of pages4 s.
    ActionAplikovaná elektronika'2000
    Event date06.09.2000-07.09.2000
    VEvent locationPlzeň
    CountryCZ - Czech Republic
    Languageeng - English
    CountryCZ - Czech Republic
    Keywordsphase locked loops ; frequency synthesizers ; Bode diagrams
    Subject RIVJA - Electronics ; Optoelectronics, Electrical Engineering
    R&D ProjectsGA102/00/0958 GA ČR - Czech Science Foundation (CSF)
    CEZAV0Z2067918 - URE-Y
    Description in EnglishThe sampled and higher order systems are discussed and means for stability checking, with the computer simulation of the Bode plots, are mentioned. It is shown that computer plotting of the PLL transfer function H(s) and 1-H(s), with the assistance of the open loop gain G(s), provides many information influence about noise of different noise sources; i.e., noise of the reference oscillator, of the voltage controlled oscillator, of the phase detector and of inevitable filters.
    WorkplaceInstitute of Radio Engineering and Electronics
    ContactPetr Vacek, vacek@ufe.cz, Tel.: 266 773 413, 266 773 438, 266 773 488
    Year of Publishing2001

Number of the records: 1  

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