0303672 - URE-Y 20000059 RIV CZ eng C - Conference Paper (international conference)
Kroupa, Věnceslav František - Štursa, Jarmil
Phase locked loops (PPL) design.
Plzeň: Vydavatelství Západočeské univerzity, 2000. ISBN 80-7082-650-9. In: Aplikovaná elektronika'2000. Sborník referátů mezinárodní konference. - (Pinker, J.), s. 99-102
[Aplikovaná elektronika'2000. Plzeň (CZ), 06.09.2000-07.09.2000]
R&D Projects: GA ČR GA102/00/0958
Institutional research plan: CEZ:AV0Z2067918
Keywords : phase locked loops * frequency synthesizers * Bode diagrams
Subject RIV: JA - Electronics ; Optoelectronics, Electrical Engineering

The sampled and higher order systems are discussed and means for stability checking, with the computer simulation of the Bode plots, are mentioned. It is shown that computer plotting of the PLL transfer function H(s) and 1-H(s), with the assistance of the open loop gain G(s), provides many information influence about noise of different noise sources; i.e., noise of the reference oscillator, of the voltage controlled oscillator, of the phase detector and of inevitable filters.
Permanent Link: http://hdl.handle.net/11104/0113859