Cepstral speech synthesis optimized for dual Hardward architecture of DSP
1.
SYSNO ASEP
0303622
Document Type
C - Proceedings Paper (int. conf.)
R&D Document Type
Conference Paper
Title
Cepstral speech synthesis optimized for dual Hardward architecture of DSP
Author(s)
Smékal, Z. (CZ) Vích, Robert (URE-Y)
Issue data
Mexico City: Universidad Nationale Autonoma de Mexico, 2000
ISBN
968-36-7762-2
Source Title
ICT-2000 International Conference on Telecommunications. Proceedings
Pages
s. 244-248
Number of pages
5 s.
Action
ICT 2000
Event date
22.05.2000-25.05.2000
VEvent location
Acapulco
Country
MX - Mexico
Language
eng - English
Country
MX - Mexico
Keywords
speech processing ; speech synthesis ; signal processing
Subject RIV
BD - Theory of Information
R&D Projects
GV102/96/K087 GA ČR - Czech Science Foundation (CSF)
CEZ
AV0Z2067918 - URE-Y
Description in English
The paper describes the realization algorithm of the cepstral IIR vocal tract model with poles and zeros, which is optimized from the viewpoint of the implementation on a fixed-point digital signal processor with dual Harvard architecture. Cepstral coefficients are used in the IIR model as coefficients of a FIR digital filter, which is introduced in the IIR digital filter instead of the delay blocks. The orders of the FIR and IIR filters depend on approximation accuracy and on sampling frequency.
